• Journal of Advanced Navigation Technology
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• v.20 no.5
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• pp.401-407
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• 2016

This paper introduces 3-dimensional path planning and guidance including power model for high altitude long endurance (HALE) UAV using solar energy. Dubins curve used in this paper has advantage of being directly available to apply path planning. However, most of the path planning problems using Dubins curve are defined in a two-dimensional plan. So, we used 3-dimensional Dubins path generation algorithm which was studied by Randal W. Beard. The aircraft model which used in this paper does not have an aileron. So we designed lateral controller by using a rudder. And then, we were conducted path tracking simulations by using a nonlinear path tracking algorithm. We generate examples according to altitude conditions. From the path tracking simulation results, we confirm that the path tracking is well on the flight path. Finally, we were modeling the power system of HALE UAVs and conducting path tracking simulation during 48hours. Modeling the amount of power generated by the solar cell through the calculation of the solar energy yield. And, we show the 48hours path tracking simulation results.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.4 s.316
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• pp.51-59
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• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) decoding which used for baseline profile and extended profile. Previous CAVLC architectures are consisted of five step block and each block gets effective bits from Controller block and Accumulator. If large number of non-zero coefficients exist, process for getting effective bits has to iterates many times. In order to reduce this unnecessary process, we propose two techniques, which combine five steps into four steps and reduce process to get efficiency bit by skipping addition step. By adopting these two techniques, the required processing time was reduced about 26% compared with previous architectures. It was designed in a hardware description language and total logic gate count was 16.83k using 0.18um standard cell library.

• Transactions of Materials Processing
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• v.17 no.8
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• pp.594-599
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• 2008

This paper presents a micro air pump based on the synthetic jet to supply reactant at the cathode side for micro fuel cells. The synthetic jet is a zero mass flux device that converts electrical energy into the momentum. The synthetic jet actuation is usually generated by a traditional PZT-driven actuator, which consists of a small cylindrical cavity, orifices and PZT diaphragms. Therefore, it is very important that the design parameters are optimized because of the simple configuration. To design the synthetic jet micro air pump, a numerical analysis has been conducted for flow characteristics with respect to various geometries. From results of numerical analysis, the micro air pump has been fabricated by the PDMS replication process. The most important design factors of the micro air pump in micro fuel cells are the small size and low power consumption. To satisfy the design targets, we used SP4423 micro chip that is high voltage output DC-AC converter to control the PZT. The SP4423 micro chips can operate from $2.2{\sim}6V$ power supply(or battery) and is capable of supplying up to 200V signals. So it is possible to make small size controller and low power consumption under 0.1W. The size of micro air pump was $16{\times}13{\times}3mm^3$ and the performance test was conducted. With a voltage of 3V at 800Hz, the air pump's flow rate was 2.4cc/min and its power consumption was only 0.15W.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.185-185
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• 2011

ZnTe semiconductor is very attractive materials for optoelectronic devices in the visible green spectral region because of it has direct bandgap of 2.26 eV. The prototypes of ZnTe light emitting diodes (LEDs) have been reported [1], showing that their green emission peak closely matches the most sensitive region of the human eye. Another application to photovoltaics proved that ZnTe is useful for the production of high-efficiency multi-junction solar cells [2,3]. By using the pulse laser deposition system, ZnTe thin films were deposited on ZnO thin layer, which is grown on (0001) Al2O3substrates. To produce the plasma plume from an ablated ZnO and ZnTe target, a pulsed (10 Hz) YGA:Nd laser with energy density of 95 mJ/$cm^2$ and wavelength of 266 nm by a nonlinear fourth harmonic generator was used. The laser spot focused on the surface of the ZnO and ZnTe target by using an optical lens was approximately 1 mm2. The base pressure of the chamber was kept at a pressure around $10^{-6}$ Torr by using a turbo molecular pump. The oxygen gas flow was controlled around 3 sccm by using a mass flow controller system. During the ZnTe deposition, the substrate temperature was $400^{\circ}C$ and the ambient gas pressure was $10^{-2}$ Torr. The structural properties of the samples were analyzed by XRD measurement. The optical properties were investigated by using the photoluminescence spectra obtained with a 325 nm wavelength He-Cd laser. The film surface and carrier concentration were analyzed by an atomic force microscope and Hall measurement system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11C
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• pp.148-156
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• 2001

This paper proposed embedded application-specific microprocessor(YS-RDSP) whose structure has an additional DSP processor on chip. The YS-RDSP can execute maximum four instructions in parallel. To make program size shorter, 16-bit and 32-bit instruction lengths are supported in YS-RDSP. The YS-RDSP provides programmability. controllability, DSP processing ability, and includes eight-kilobyte on-chip ROM and eight-kilobyte RAM. System controller on the chip gives three power-down modes for low-power operation, and SLEEP instruction changes operation statue of CPU core and peripherals. YS-RDSP processor was implemented with Verilog HDL on top-down methodology, and it was improved and verified by cycle-based simulator written in C-language. The verified model was synthesized with 0.7um, 3.3V CMOS standard cell library, and the layout size was 10.7mm78.4mm which was implemented by using automatic P&R software.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.8A
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• pp.785-793
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• 2007

This paper presents the digital signal processing submodule of a 100Base-TX Ethernet receiver to support 100Mbps at TP cable channel. The proposed submodule consists of programmable gain controller, timing recovery, adaptive equalizer and baseline wander compensator. The measured Bit Error Rate is less than $10^{-12}BER$ when continuously receiving data up to 150m. The proposed signal processing submodule is implemented in digital circuits except for PLL and amplifier. The performance improvement of the proposed equalizer and BLW compensator is measured about 1dB compared with the existing architecture that removes BLW using errors of an adaptive equalizer. The architecture has been modeled using Verilog-HDL and synthesized using samsung $0.18{\mu}m$ cell library. The implemented digital signal processing submodule operates at 142.7 MHz and the total number of gates are about 128,528.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.3
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• pp.258-265
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• 2011

This paper presents a variable frequency current control scheme for the air-pressure control of diaphragm. Differ from the conventional air-pressure control of diaphragm, the proposed method uses a single-phase inverter to control the phase current and frequency. The phase current is adjusted to keep the reference air-pressure of the diaphragm. And the current frequency is changed to reduce the mechanical vibration. In order to smooth change of the operation with a constant air-pressure, the frequency is changed according to the voltage reference from the current controller. When the phase current is satisfied to the constant air-pressure, the current frequency is increased to reduce the vibration of the diaphragm. When the reference voltage to keep the phase current is over than the set value, the current frequency is decreased to keep the air-pressure. The proposed control scheme is verified by the experimental test of a commercial diaphragm.

• Journal of Power Electronics
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• v.17 no.3
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• pp.821-834
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• 2017

This paper reports on a single-inductor multiple-output step-up converter with digital control. A systematic analog-to-digital-controller design is explained. The number of digital blocks in the feedback path of the proposed converter has been decreased. The simpler digital pulse-width modulation (DPWM) architecture is then utilized to reduce the power consumption. This architecture has several advantages because counters and a complex digital design are not required. An initially designed unit-delay cell is adopted recursively for the construction of coarse, intermediate, and fine delay blocks. A digital limiter is then designed to allow only useful code for the DPWM. The input voltage is 1.8 V, whereas output voltages are 2 V and 2.2 V. A co-simulation was also conducted utilizing PowerSim and Matlab/Simulink, whereby the 55 nm process was employed in the experimental results to evaluate the performance of the architecture.

• The Journal of the Convergence on Culture Technology
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• v.5 no.3
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• pp.263-269
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• 2019

In this study, the characteristics and operation of a multi-purpose loader equipped with various sensors such as a sensor capable of measuring the boom length, an angle sensor capable of measuring the tilt of the left and right sides of the boom and the loader, and a load cell capable of measuring the weight during lifting We have implemented a system that displays related data values. The configuration of the system reads the values from the sensors, sends them to the vehicle controller, and transmits the calculated results of the overturn rate and other important information to the display device using the CANOpen protocol. Also, in the calculation of the overturn ratio, the structure of the multi-purpose loader is similar to that of the crane belonging to the heavy equipment, and the crane overturn rate calculation method is used. Through this study, we can observe the condition of the heavy equipment and recognize the emergency situations such as abalone through the display device.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.36 no.3
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• pp.343-350
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• 2012

A planar solid oxide fuel cell (PSOFC) is studied in its application in a high-temperature stationary power plant. Even though PSOFCs with external reformers are designed for application from the distributed power source to the central power plant, such PSOFCs may sacrifice more system efficiency than internally reformed SOFCs. In this study, modeling of the PSOFC with an external reformer was developed to analyze the feasibility of thermal energy utilization for the external reformer. The PSOFC system model includes the stack, reformer, burner, heat exchanger, blower, pump, PID controller, 3-way valve, reactor, mixer, and steam separator. The model was developed under the Matlab/Simulink environment with Thermolib$^{(R)}$ modules. The model was used to study the system performance according to its configuration. Three configurations of the SOFC system were selected for the comparison of the system performance. The system configuration considered the cathode recirculation, thermal sources for the external reformer, heat-up of operating gases, and condensate anode off-gas for the enhancement of the fuel concentration. The simulation results show that the magnitude of the electric efficiency of the PSOFC system for Case 2 is 12.13% higher than that for Case 1 (reference case), and the thermal efficiency of the PSOFC system for Case 3 is 76.12%, which is the highest of all the cases investigated.