• Title/Summary/Keyword: carrier film

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산소분압에 따른 IGZO 박막트랜지스터의 특성변화 연구

  • Han, Dong-Seok;Gang, Yu-Jin;Park, Jae-Hyeong;Yun, Don-Gyu;Park, Jong-Wan
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.02a
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    • pp.497-497
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    • 2013
  • Semiconducting amorphous InGaZnO (a-IGZO) has attracted significant research attention as improved deposition techniques have made it possible to make high-quality a-IGZO thin films. IGZO thin films have several advantages over thin film transistors (TFTs) based on other semiconducting channel layers.The electron mobility in IGZO devices is relatively high, exceeding amorphous Si (a-Si) by a factor of 10 and most organic devices by a factor of $10^2$. Moreover, in contrast to other amorphous semiconductors, highly conducting degenerate states can be obtained with IGZO through doping, yet such a state cannot be produced with a-Si. IGZO thin films are capable of mobilities greaterthan 10 $cm^2$/Vs (higher than a-Si:H), and are transparent at visible wavelengths. For oxide semiconductors, carrier concentrations can be controlled through oxygen vacancy concentration. Hence, adjusting the oxygen partial pressure during deposition and post-deposition processing provides an effective method of controlling oxygen concentration. In this study, we deposited IGZO thinfilms at optimized conditions and then analyzed the film's electrical properties, surface morphology, and crystal structure. Then, we explored how to generate IGZO thin films using DC magnetron sputtering. We also describe the construction and characteristics of a bottom-gate-type TFT, including the output and transfer curves and bias stress instability mechanism.

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Carbon nanotube/silicon hybrid heterojunctions for photovoltaic devices

  • Castrucci, Paola
    • Advances in nano research
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    • v.2 no.1
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    • pp.23-56
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    • 2014
  • The significant growth of the Si photovoltaic industry has been so far limited due to the high cost of the Si photovoltaic system. In this regard, the most expensive factors are the intrinsic cost of silicon material and the Si solar cell fabrication processes. Conventional Si solar cells have p-n junctions inside for an efficient extraction of light-generated charge carriers. However, the p-n junction is normally formed through very expensive processes requiring very high temperature (${\sim}1000^{\circ}C$). Therefore, several systems are currently under study to form heterojunctions at low temperatures. Among them, carbon nanotube (CNT)/Si hybrid solar cells are very promising, with power conversion efficiency up to 15%. In these cells, the p-type Si layer is replaced by a semitransparent CNT film deposited at room temperature on the n-doped Si wafer, thus giving rise to an overall reduction of the total Si thickness and to the fabrication of a device with cheaper methods at low temperatures. In particular, the CNT film coating the Si wafer acts as a conductive electrode for charge carrier collection and establishes a built-in voltage for separating photocarriers. Moreover, due to the CNT film optical semitransparency, most of the incoming light is absorbed in Si; thus the efficiency of the CNT/Si device is in principle comparable to that of a conventional Si one. In this paper an overview of several factors at the basis of this device operation and of the suggested improvements to its architecture is given. In addition, still open physical/technological issues are also addressed.

Physical Characteristics of 3C-SiC Thin-films Grown on Si(100) Wafer (Si(100) 기판 위에 성장돈 3C-SiC 박막의 물리적 특성)

  • ;;Shigehiro Nishino
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.15 no.11
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    • pp.953-957
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    • 2002
  • Single crystal 3C-SiC (cubic silicon carbide) thin-films were deposited on Si(100) wafer up to the thickness of 4.3 ${\mu}{\textrm}{m}$ by APCVD (atmospheric pressure chemical vapor deposition) method using HMDS (hexamethyildisilane; {CH$_{3}$$_{6}$ Si$_{2}$) at 135$0^{\circ}C$. The HMDS flow rate was 0.5 sccm and the carrier gas flow rate was 2.5 slm. The HMDS flow rate was important to get a mirror-like crystal surface. The growth rate of the 3C-SiC film was 4.3 ${\mu}{\textrm}{m}$/hr. The 3C-SiC epitaxial film grown on Si(100) wafer was characterized by XRD (X-ray diffraction), AFM (atomic force microscopy), RHEED (reflection high energy electron diffraction), XPS (X-ray photoelecron spectroscopy), and Raman scattering, respectively. Two distinct phonon modes of TO (transverse optical) near 796 $cm^{-1}$ / and LO (longitudinal optical) near 974$\pm$1 $cm^{-1}$ / of 3C-SiC were observed by Raman scattering measurement. The heteroepitaxially grown film was identified as the single crystal 3C-SiC phase by XRD spectra (2$\theta$=41.5。).).

LCD Driver IC Assembly Technologies & Status

  • Shen, Geng-shin
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2002.09a
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    • pp.21-30
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    • 2002
  • According the difference of flex substrate, (reel tape), there are three kind assembly types of LCD driver IC is COG, TCP and COF, respectively. The TCP is the maturest in these types for stability of raw material supply and other specification. And TCP is the major assembly type of LCD driver IC and the huge demand from Taiwan's large TFT LCD panel house since this spring. But due to its package structure and the raw material applied in this package, there is some limitation in fine pitch application of this package type, (TCP). So, COF will be very potential in compact and portable application comparison with TCP in the future. There are three kinds assembly methods in COF, one is ACF by using the anisotropic conductive film to connect the copper lead of tape and gold bump of IC, another is eutectic bonding by using the thermo-pressure to joint the copper lead of tape and gold bump of IC, and last is NCP by using non-conductive paste to adhere the copper lead of tape and gold bump of IC. To have a global realization, this paper will briefly review the status of Taiwan's large TFT panel house, the internal driver IC design house, and the back-end assembly house in the beginning. The different material property of raw material, PI tape is also compared in the paper. The more detail of three kinds of COF assembly method will be described and compared in this paper.

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Improvement of COF Bending-induced Lead Broken Failure in LCD Module (LCD Module내 COF Bending에 따른 Lead Broken Failure의 개선)

  • Shim, Boum-Joo;Choi, Yeol;Yi, Jun-Sin
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.21 no.3
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    • pp.265-271
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    • 2008
  • TCP(Tape Carrier Package), COG (Chip On Glass), COF(Chip On Film) are three methods for connecting LDI(LCD Driver IC) with LCD panels. Especially COF is growing its portion of market place because of low cost and fine pitch correspondence. But COF has a problem of the lead broken failure in LCD module process and the usage of customer. During PCB (Printed Circuit Board) bonding process, the mismatch of the coefficient of thermal expansion between PCB and D-IC makes stress-concentration in COF lead, and also D-IC bending process during module assembly process makes the level of stress in COF lead higher. As an affecting factors of lead-broken failure, the effects of SR(Solder Resister) coating on the COF lead, surface roughness and grain size of COF lead, PI(Polyimide) film thickness, lead width and the ACF(Anisotropic Conductive Film) overlap were studied, The optimization of these affecting manufacturing processes and materials were suggested and verified to prevent the lead-broken failure.

Characteristics of Sputtering Mo Doped Carbon Films and the Application as the Gate Electrode in Organic Thin Film Transistor (스퍼터링 Mo 도핑 탄소박막의 특성과 유기박막트랜지스터의 게이트 전극으로 응용)

  • Kim, Young Gon;Park, Yong Seob
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.30 no.1
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    • pp.23-26
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    • 2017
  • Mo doped carbon (C:Mo) thin films were fabricated with various Mo target power densities by unbalanced magnetron sputtering (UBM). The effects of target power density on the surface, structural, and electrical properties of C:Mo films were investigated. UBM sputtered C:Mo thin films exhibited smooth and uniform surfaces. However, the rms surface roughness of C:Mo films were increased with the increase of target power density. Also, the resistivity value of C:Mo film as electrical properties was decreased with the increase of target power density. From the performance of organic thin filml transistor using conductive C:Mo gate electrode, the carrier mobility, threshold voltage, and on/off ratio of drain current (Ion/Ioff) showed $0.16cm^2/V{\cdot}s$, -6.0 V, and $7.7{\times}10^4$, respectively.

High rate deposition and mechanical properties of SiOx film on PET and PC polymers by PECVD with the dual frequencies UHF and HF at low temperature

  • Jin, Su-B.;Choi, Yoon-S.;Choi, In-S.;Han, Jeon-G.
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.08a
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    • pp.180-180
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    • 2010
  • The design and implementation of high rate deposition process and anti-scratch property of silicon oxide film by PECVD with UHF power were investigated according to the effect of UHF input power with HF bias. New regime of high rate deposition of SiOx films by hybrid plasma process was investigated. The dissociation of OMCTS (C8H24Si4O4) precursor was controlled by plasma processes. SiOx films were deposited on polyethylene terephthalate (PET) and polycarbonate substrate by plasma enhanced chemical vapor deposition (PECVD) using OMCTS with oxygen carrier gas. As the input energy increased, the deposition rate of SiOx film increased. The plasma diagnostics were performed by optical emission spectrometry. The deposition rate was characterized by alpha-step. The mechanical properties of the coatings were examined by nano-indenter and pencil hardness, respectively. The deposition rate of the SiOx films could be controlled by the appropriate intensity of excited neutrals, ionized atoms and UHF input power with HF bias at room temperature, as well as the dissociation of OMCTS.

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Electrical Characteristics of Solution-processed Cu(In,Ga)S2 Thin Film Solar Cells (용액 공정으로 만든 Cu(In,Ga)S2 박막태양전지의 전기적 특성)

  • Kim, Ji Eun;Min, Byoung Koun;Kim, Dong-Wook
    • Current Photovoltaic Research
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    • v.2 no.2
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    • pp.69-72
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    • 2014
  • We investigated current-voltage (I-V) and capacitance (C)-V characteristics of solution-processed thin film solar cells, consisting of $Cu(In,Ga)S_2$ and $CuInS_2$ stacked absorber layers. The ideality factors, extracted from the temperature-dependent I-V curves, showed that the tunneling-mediated interface recombination was dominant in the cells. Rapid increase of both series- and shunt-resistance at low temperatures would limit the performance of the cells, requiring further optimization. The C-V data revealed that the carrier concentration of the $CuInS_2$ layer was about 10 times larger than that of the $Cu(In,Ga)S_2$ layer. All these results could help us to find strategies to improve the efficiency of the solution-processed thin film solar cells.

Effect of oxalic acid solution to optimize texturing of the front layer of thin film sloar cells

  • Park, Hyeong-Sik;Jang, Gyeong-Su;Jo, Jae-Hyeon;An, Si-Hyeon;Jang, Ju-Yeon;Song, Gyu-Wan;Lee, Jun-Sin
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.401-401
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    • 2011
  • In this work, we deposited Al2O3doped ZnO (AZO) thin films by direct current (DC) magnetron sputtering method with a $40^{\circ}$ tilted target, for application in the front layer of thin film solar cell. Wet chemical etching behavior of AZO films was also investigated. In order to optimize textured AZO films, oxalic acid ($C_2H_2O_4$)has been used as wet etchant of AZO film. In this experiment we used 0.001% concentration of oxalic acid various etching time, that showed an anisotropy in etching texture of AZO films. Electrical resistivity, Hall mobility and carrier concentration measurements are performed by using the Hall measurement, that are $6{\times}10^{-4}{\Omega}cm$, $20{\sim}25cm^2/V-s$ and $4{\sim}6{\times}10^{20}$, respectively.

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Degradation of Ultra-thin SiO2 film Incorporated with Hydrogen or Deuterium Bonds during Electrical Stress (수소 및 중수소가 포함된 실리콘 산화막의 전기적 스트레스에 의한 열화특성)

  • Lee, Jae-sung;Back, Jong-mu;Jung, Young-chul;Do, Seung-woo;Lee, Yong-hyun
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.18 no.11
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    • pp.996-1000
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    • 2005
  • Experimental results are presented for the degradation of 3 nm-thick gate oxide $(SiO_2)$ under both Negative-bias Temperature Instability (NBTI) and Hot-carrier-induced (HCI) stresses using P and NMOSFETS, The devices are annealed with hydrogen or deuterium gas at high-pressure $(1\~5\;atm.)$ to introduce higher concentration in the gate oxide. Both interface trap and oxide bulk trap are found to dominate the reliability of gate oxide during electrical stress. The degradation mechanism depends on the condition of electrical stress that could change the location of damage area in the gate oxide. It was found the trap generation in the gate oxide film is mainly related to the breakage of Si-H bonds in the interface or the bulk area. We suggest that deuterium bonds in $SiO_2$ film are effective in suppressing the generation of traps related to the energetic hot carriers.