• Asian Pacific Journal of Cancer Prevention
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• 제16권17호
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• pp.7749-7754
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• 2015

Background: Currently, cationic liposome has become the commonly used vehicles for gene transfection. Furthermore, one of the most significant steps in microRNAs expression studies is transferring microRNAs into cell cultures successfully. In this study we aim to approach the feasibility of transfection of cervical cancer cell lines mediated by liposome and to obtain the optimized transfection condition for cervical cancer cell lines. Materials and Methods: $Lipofectamine^{TM}2000$ as the carrier, miR-101 mimic was transfected into Hela cells and Siha cells. Using green fluorescent protein as reporter gene, to set different groups according to cell seeding density, the amount of miRNA, miRNA and the proportion of Liposomes, Whether to add serum into medium to study their impact on the liposomal transfection efficiency. Finally, MTT assay was used to analyze the relative minimal cell toxicity of liposome reagents. Results: The seeding density of Hela cell line and Siha are $1.5{\times}10^4$ (per well of 24 well plates), miRNA amount is 1ul of both, the ratio of miRNA and liposome is 1:0.5 of Hela cell line; 1:0.7 of Siha cell line respectively, after 24 hours we can get the highest transfection efficiency. Compared with serum medium, only Siha cells cultured with serum-free medium obtained higher transfection efficiency before transfection (P<0.01). MTT assay showed that according to the above conditions which has the lowest cytotoxicity. Conclusions: The method of Liposome to transfected is a suitable way and it can be an efficient reagent for miRNA delivery for Hela cells and Siha cells in vitro. It may serve as a reference for the further research or application.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• 한국태양에너지학회 논문집
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• 제25권4호
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• pp.1-11
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• 2005

The stoichiometric mixture of evaporating materials for the $CuInSe_2$ single crystal thin film was prepared from horizontal furnace. Using extrapolation method of X-ray diffraction patterns for the polycrystal $CuInSe_2$, it was found tetragonal structure whose lattice constant $a_0$ and $c_0$ were $5.783\;{\AA}$ and $11.621\;{\AA}$, respectively. To obtain the $CuInSe_2$ single crystal thin film, $CuInSe_2$ mixed crystal was deposited on throughly etched GaAs(100) by the HWE(Hot Wall Epitaxy) system. The source and substrate temperature were $620^{\circ}C$ and $410^{\circ}C$ respectively. The crystalline structure of $CuInSe_2$ single crystal thin film was investigated by the double crystal X-ray diffraction(DCXD). Hall effect on this sample was measured by the method of Van der Pauw and studied on carrier density and mobility depending on temperature. From Hall data, the mobility was likely to be decreased by impurity scattering in the temperature range 30 K to 100 K and by lattice scattering in the temperature range 100 K to 293 K. The temperature dependence of the energy band gap of the $CuInSe_2$ obtained from the absorption spectra was well described by the Varshni's relation, $E_g(T)=1.1851\;eV-(8.99{\times}10^{-4}\;eV/K)T^2/(T+153\;K)$. The open-circuit voltage, short current density, fill factor, and conversion efficiency of $n-CdS/p-CuGaSe_2$ heterojunction solar cells under $80\;mW/cm^2$ illumination were found to be 0.51V, $29.3\;mA/cm^2$, 0.76 and 14.3 %, respectively.

• 한국태양에너지학회 논문집
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• 제38권1호
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• pp.25-36
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• 2018

The stoichiometric mixture of evaporating materials for the $CaAl_2Se_4$: Co single crystal thin film was prepared from horizontal furnace. Using extrapolation method of X-ray diffraction patterns for the polycrystal $CaAl_2Se_4$, it was found orthorhomic structure whose lattice constant $a_0$, $b_0$ and $c_0$ were 6.4818, $11.1310{\AA}$ and $11.2443{\AA}$, respectively. To obtain the $CaAl_2Se_4$: Co single crystal thin film, $CaAl_2Se_4$: Co mixed crystal was deposited on throughly etched Si (100) by the HWE (Hot Wall Epitaxy) system. The source and substrate temperature were $600^{\circ}C$ and $440^{\circ}C$ respectively. The crystalline structure of $CaAl_2Se_4$: Co single crystal thin film was investigated by the double crystal X-ray diffraction (DCXD). Hall effect on this sample was measured by the method of Van der Pauw and studied on carrier density and mobility depending on temperature. From Hall data, the mobility was likely to be decreased by impurity scattering in the temperature range 30 K to 100 K and by lattice scattering in the temperature range 100 K to 293 K. The temperature dependence of the energy band gap of the $CaAl_2Se_4$: Co obtained from the absorption spectra was well described by the Varshni's relation, $E_g(T)=3.8239eV-(4.9823{\times}10^{-3}eV/K)T_2/(T+559K)$. The open-circuit voltage, short current density, fill factor, and conversion efficiency of $p-Si/p-CaAl_2Se_4$: Co heterojunction solar cells under $80mW/cm^2$ illumination were found to be 0.42 V, $25.3mA/cm^2$, 0.75 and 9.96%, respectively.

• Electronic Materials Letters
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• 제14권6호
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• pp.689-699
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• 2018

Nanostructured Ni doped $Bi_2S_3$ ($Bi_{2-x}Ni_xS_3$, $0{\leq}x{\leq}0.07$) is explored as a candidate for telluride free thermoelectric material, through a combination process of mechanical alloying with subsequent consolidation by cold pressing followed with a sintering process. The cold pressing method was found to impact the thermoelectric properties in two ways: (1) introduction of the dopant atom in the interstitial sites of the crystal lattice which results in an increase in carrier concentration, and (2) introduction of a porous structure which reduces the thermal conductivity. The electrical resistivity of $Bi_2S_3$ was decreased by adding Ni atoms, which shows a minimum value of $2.35{\times}10^{-3}{\Omega}m$ at $300^{\circ}C$ for $Bi_{1.99}Ni_{0.01}S_3$ sample. The presence of porous structures gives a significant effect on reduction of thermal conductivity, by a reduction of ~ 59.6% compared to a high density $Bi_2S_3$. The thermal conductivity of $Bi_{2-x}Ni_xS_3$ ranges from 0.31 to 0.52 W/m K in the temperature range of $27^{\circ}C$ (RT) to $300^{\circ}C$ with the lowest ${\kappa}$ values of $Bi_2S_3$ compared to the previous works. A maximum ZT value of 0.13 at $300^{\circ}C$ was achieved for $Bi_{1.99}Ni_{0.01}S_3$ sample, which is about 2.6 times higher than (0.05) of $Bi_2S_3$ sample. This work show an optimization pathway to improve thermoelectric performance of $Bi_2S_3$ through Ni doping and introduction of porosity.

• 한국산학기술학회논문지
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• 제20권3호
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• pp.29-34
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• 2019

SiC는 큰 에너지 밴드 갭을 갖고, 불순물 도핑에 의해 p형 및 n형 전도의 제어가 용이해서 고온용 전자부품 소재로 활용이 가능한 재료이다. 특히 $N_2$ 분위기, $2000^{\circ}C$에서 ${\beta}-SiC$ 분말로부터 제조한 다공질 n형 SiC 반도체의 경우, $800{\sim}1000^{\circ}C$에서의 도전율 값이 단결정 SiC와 비교해서 비슷하거나 오히려 높은 값을 나타내었으며, 반면에 열전도율은 치밀한 SiC 세라믹스와 비교시 1/10~1/30 정도로 낮은 값을 나타내었다. 본 연구에서는 소결온도를 낮추기 위해 n형 ${\beta}-SiC$에 함침 시킨 polycarbosilane (PCS)의 열분해에 의한 반응소결 공정 ($1400{\sim}1600^{\circ}C$)으로 다공질 소결체를 제작하였다. 함침 및 소결공정($N_2$ 분위기, $1600^{\circ}C$, 3시간)을 반복함에 따라 상대밀도는 크게 증가하지 않았지만 Seebeck 계수 및 도전율은 크게 증가하였다. 본 연구에서의 열전변환 효율을 반영하는 power factor는 고온에서 상압소결 공정으로 제작한 다공질 SiC 반도체에 비해 1/100~1/10 정도 작게 나타났지만, 미세구조 및 캐리어 밀도를 정밀하게 제어하면, 본 연구에서의 반응소결 공정으로 제작한 SiC 반도체의 열전물성은 크게 향상될 것으로 판단된다.

• 한국산학기술학회논문지
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• 제22권3호
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• pp.13-19
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• 2021

n형 SiC 반도체에서 적층 결함이 열전 물성에 미치는 영향에 대해 연구하였다. ��-SiC 분말 성형체를 질소 분위기에서 1600~2100 ℃, 20~120분간 열처리해서 30~42 %의 기공률을 갖는 다공질 SiC 반도체를 제작하였다. X선 회절 분석으로 적층 결함량, 격자 스트레인 및 격자 상수를 산출하였고, 미세 구조 분석을 위해서 기공률 및 비표면적 측정과 함께, 주사 전자현미경 (SEM), 투과 전자현미경 (TEM) 및 고분해능 전자현미경 (HREM) 등을 관찰하였다. Ar 분위기 550~900 ℃에서 도전율과 Seebeck 계수를 측정 및 산출하였다. 열처리 온도가 높을수록, 처리 시간이 길어질수록 캐리어 농도 증가 및 입자와 입자간의 연결성 향상에 의해 도전율이 향상되었다. 도너로 작용하는 질소의 고용으로 Seebeck 계수는 음(-)의 값을 나타내었고, 도전율과 마찬가지로 열처리 온도 및 시간이 상승함에 따라 Seebeck 계수의 절대 값이 증가하였다. 이는 적층 결함의 감소, 즉 입자 및 결정 성장과 함께 적층 결함 밀도의 감소에 의해 포논의 평균 자유 행정이 증가해서 결과적으로 포논-드랙 효과에 의한 Seebeck 계수의 향상으로 나타난 것으로 판단된다.

• 한국결정성장학회지
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• 제9권2호
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• pp.197-206
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• 1999

수평 전기로에서 $AgInSe_2$다결정을 합성하여 HWE(Hot Wall Epitaxy) 방법으로 $AgInSe_2$ 단결정 박막을 반절연성 GaAs(100) 위에 성장하였다. $AgInSe_2$단결정 박막은 증발원과 기판의 온도를 각각 $610^{\circ}C$, $450^{\circ}C$로 성장하였다. 이때 성장된 단결정 박막의 두께는 3.8$\mu\textrm{m}$였다. 단결정 박막의 결정성의 조사에서 20 K에서 측정한 광발광 스펙트럼은 884.1nm(1.4024eV) 근처에서 excition emission 스펙트럼이 가장 강하게 나타났으며, 또한 이중결정 X-선 회절곡선(DCXD)의 반폭치(FWHM)도 125arcsec로 매우 작은 값으로 측정되어 최적 성장 조건임을 알 수 있었다. Hall 효과는 van der Pauw 방법에 의해 측정되었으며, 온도에 의존하는 운반자 농도와 이동도는 293K에서 각각 $9.58{\times}10^{22} electron/m^3,\; 3.42{\times}10^{-2}m^2/V{\cdot}s$였다. $AgInSe_2$단결정 박막의 광전류 단파장대 봉우리들로부터 20K에서 측정된 $\Delta$Cr(Crystal field splitting)은 0.12eV, $\Delta$So(spin orbit coupling)는 0.29 eV였다. 20K에서 얻어진 광발광 봉우리들 중에서 881.1nm(1.4071 eV)와 882.4nm(1.4051 eV)는 free exciton$E_x$의 upper polariton과 lower polariton인$E_x^U$와 $E_x^L$를 의미하며, 884.1nm(1.4024 eV)는 donor-bound exciton emission에 의한 $I_2$봉우리를, 885.9nm(1.3995 eV)는 acceptor-bound exciton emission에 의한 $I_1$ 봉우리를 각각 나타내었다. 또한 887.5nm(1.3970 eV)에서 관측된 봉우리는 DAP(donor-acceptor pair)에 기인하는 광발광 봉우리로 해석되었다.

• 한국결정성장학회지
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• 제21권3호
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• pp.99-104
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• 2011

단결정 성장을 위한 $MgGa_2Se_4$ 다결정은 수평 전기로에서 합성하였으며, 결정구조는 rhombohedral이고 격자상수 $a_0$는 3.953 ${\AA}$, $c_0$는 38.890 ${\AA}$였다. $MgGa_2Se_4$ 단결정박막은 HWE(Hot Wall Epitaxy) 방법으로 반절연성 GaAs(100)기판에 성장시켰다. 단결정박막의 성장 조건은 증발원의 온도 $610^{\circ}C$, 기판의 온도 $400^{\circ}C$에서 진행되었으며 성장 속도는 0.5 ${\mu}m/h$였다. 단결정박막의 결정성은 이중 결정 x-선 회절곡선의 반폭치와 X-선 회절무늬의 ${\omega}-2{\theta}$로부터 구하여 최적 성장 조건을 알 수 있었다. Hall 효과는 van der Pauw 방법에 의해 측정되었으며, 온도에 의존하는 운반자 농도와 이동도는 293 K에서 각각 $6.21{\times}10^{18}/cm^3$, 248 $cm^2/v{\cdot}s$였다. $MgGa_2Se_4$/SI(Semi-Insulated) GaAs(100) 단결정 박막의 광흡수 스펙트럼을 10 K에서 293 K까지 측정하였다. 광흡수 스펙트럼으로부터 구한 에너지 갭 $E_g(T)$는 varshni 공식 $E_g(T)=E_g(0)=({\alpha}T^2/T+{\beta})$을 잘 만족함을 알 수 있었다. 여기서 $E_g(0)=2.34\;eV$, ${\alpha}=8.81{\times}10^{-4}\;eV/K$, ${\beta}=251\;K$였다.

• 한국결정성장학회지
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• 제10권6호
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• pp.425-433
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• 2000

수평 전기로에서 $CuGaTe_2$다결정을 합성하여 HWE 방법으로 $CuGaTe_2$단결정 박막을 반절연성 GaAs (100) 위에 성장하였다. $CuGaTe_2$단결정 박막은 증발원과 기판의 온도를 각각 $670^{\circ}C$, $410^{\circ}C$로 성장하였다. 이때 단결정 박막의 결정성이 10K에서 측정한 광발광 스펙트럼은 954.5 nm(1.2989 eV) 근처에서 exciton emission 스펙트럼이 가장 강하게 나타났으며, 또한 이중결정 X-선 요동곡선(DCRC)의 반폭치(FWHM)도 139arcsec로 가장 작게 측정되어 최적 성장 조건임을 알 수 있었다. Hall효과는 van der Pauw 방법에 의해 측정되었으며, 온도에 의존하는 운반자 농도와 이동도는 293 K에서 각각 $8.72{\times}10{23}$개 $\textrm m^3$, $3.42{\times}10^{-2}$ $\textrm m^2$/V.s였다. 상온에서 $CuGaTe_2$단결정 박막의 광흡수 특성으로부터 에너지 띠간격이 1.22 eV였다. Bandedge에 해당하는 광전도도 peak의 온도 의존성은 varshni 관계식으로 설명되었으며, varshni 관계식의 상수값은 $E_g$(0) = 1.3982 eV, $\alpha$ = $4.27{\times}10^{-4}$eV/K, $\beta$ = 265.5K로 주어졌다. $CuGaTe_2$단결정 박막의 광전류 단파장대 봉우리들로부터 10K에서 측정된$\Delta$cr(crystal field splitting)은 0.0791 eV, $\Delta$s.o(spin orbit coupling)는 0.2463 eV였다. 10K에서 광발광 봉우리의 919.8nm(1.3479 eV) free exciton($E_x$), 954.5nm(1.2989 eV)는 donor-bound exciton 인 $I_2(D^0,X)$와 959.5nm(1.2921 eV)는 acceptor-bound exciton 인 $I_1(A_0, X)$이고, 964.6nm(1.2853 eV)는 donor-acceptor pair(DAP) 발광, 1341.9nm(0.9239 eV)는 self activated(SA)에 기인하는 광발광 봉우리로 고찰되었다.