• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.514-519
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• 2001

Most of inverters adopt a diode rectifier as an input stage, which has very simple and rugged structure and therefore low cost. In order to properly design the 3-phase diode rectifier with an output smoothing capacitor and input inductors, it is necessary to fully simulate the system due to its nonlinear characteristics. Therefore this paper describes the operating behaviors including the current commutation in detail by using the proposed equivalent circuit, and also proposes the Simulink-based model of the system. The simulation results show the validity of the proposed model in all operating conditions.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.33 no.11
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• pp.456-463
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• 1984

The fast-rising high-voltage pulse generation circuit system of a theta pinch is both theoretically and experimentally investigated. The idealized model of this circuit system is a hybrid circuit system composed of three parts: a lumped circuit part being consisted of a capacitor bank and a spark switch connected in series, another lumped circuit part being consisted of the Blumlein transmission line, whose end load is the pinch coil. the voltage difference between two ends of the pinch coil is formulated by analyzing this hybrid circuit system by means of the law of the signal propagation in the transmission line and Kirchhoff's laws. The expedient numerical method for computer calculation is developed to generate the pulse profile of the voltage difference across the pinch coil. The period of the experimentally measured main pulse is a fourth of the theoretical one neglecting the resistance of the pinch coil. We attribute this discrepancy to the modelling in the theoretical calculation that hte resistance and inductance of the spark switch and capacitor bank are assumed to be constant through discharge. Therefore, we can see that the rise time of the imploding magnetic-field pulse is mainly dependent on the spark switch and capacitor bank.

• Journal of IKEEE
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• v.23 no.2
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• pp.474-478
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• 2019

In this paper, we analyze the degradation of receiving sensitivity due to the coupling between digital noise and mobile handset antenna using characteristic mode. First, we analyze the coupling mechanism between the antenna and digital noise, and analyze the role of the decoupling capacitor of the ground signal line, which is one of the ways to improve the antenna receiving sensitivity degradation due to camera noise. For the analysis, the digital signal line and the ground line of the FPCB of the camera module are modeled as a loop type feeder that excites the characteristic mode of the PCB ground, and improved model which has a ground line with a capacitor are analyzed.

• Journal of Power Electronics
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• v.19 no.1
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• pp.24-33
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• 2019

A new modeling method for AC-AC switched capacitor converters (SCCs) is introduced in this study. The proposed analytical method aims to accurately describe the input-output characteristics of AC-AC SCCs and establish a mathematical model for static voltage conversion ratio and equivalent resistance, which are key performance metrics for SCCs. A quantitative analysis of converter regulation capability is addressed on the basis of the modeling method. In this analysis, the effects of the control parameters and individual components on SCCs are illustrated extensively. Component stresses, such as the peak value and transient variation of the voltage/current of the converter, are also presented. The effectiveness of the proposed method is verified by comparing it with the existing modeling method and applying it to an AC-AC SCC with a conversion ratio of three. Two 1 kW prototypes are built in a laboratory, and their experimental results exhibit good agreement with the theoretical analysis.

• Korean Journal of Materials Research
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• v.32 no.7
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• pp.313-319
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• 2022

Double-layer capacitors (DLCs) are developed with high surface electrodes to achieve a high capacitance value. In the present work, the initial bulk concentration of 1 mol/m³ and 3 mol /m³ are selected to show the consequential effects on the performance of a double-layer capacitor. A 1D model of COMSOL Multiphysics has been developed to analyze the electric field and potential in cell voltage, the electric displacement field and polarization induced by the field, and energy density in a double-layer structure. The electrostatics and the electric circuit modes in COMSOL are used to simulate the electrochemical processes in the double-layer structure. The analytical analysis of a double-layer capacitor with different initial bulk concentrations is investigated by using Poisson-Nernst-Plank equations. From the simulation results, the differential capacitance changes as a function of compact layer thickness and initial bulk concentration. The energy density varies with the differential capacitance and voltage window. The values of energy density are dominated by the interaction of ions in the solution and electrode surface.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.2
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• pp.1051-1058
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• 2014

This paper presents a Electrical characteristics of the Memristor device using the PSPICE for circuit analysis. After making macro model of the Memristor device for circuit analysis, electric characteristics of the model such as time analysis, frequency and DC analysis according to the input voltage were performed by PSPICE simulation. Also, we made simple circuits of memristor series and parallel structure and analyzed the simulated SPICE results. Finally, we made a memristor-capacitor (M-C) circuit. charge and discharge characteristics were analyzed. In case of input pulse signal of 250 Hz, the Memristor-capacitor circuit showed delay time of 0.6ms, rising time of 0.58 ms and falling time of 1.6 ms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.146-153
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• 2008

In this paper, a integrated phase-locked loop(PLL) as a clock multiphase generator for a high speed serial link is designed. The designed PLL keeps the same bandwidth and damping factor by using programmable current mirror in the whole operation frequency range. Also, the close-loop transfer function and VCO's phase-noise transfer function of the designed PLL are obtained with circuit netlists. The self impedance on board-mounted chip is calculated according to sizes and positions of decoupling capacitors. Especially, the detailed self-impedance analysis is carried out between frequency ranges represented the maximum gain in the close-loop transfer function and the maximum gain in the VCO's phase noise transfer function. We shows PLL's jitter characteristics by decoupling capacitor's sizes and positions from this result. The designed PLL has the wide operating range of 0.4GHz to 2GHz in operating voltage of 1.8V and it is designed 0.18-um CMOS process. The reference clock is 100MHz and PLL power consumption is 17.28mW in 1.2GHz.

• Journal of IKEEE
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• v.22 no.2
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• pp.258-265
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• 2018

This paper proposes an algorithm for reducing the starting current when the single-phase induction motor starts and analyzes its operation. Generally, the single-phase induction motors require several starters to generate the starting torque due to their structural characteristics. In this paper, a capacitor-start / capacitor-run method of the single-phase induction motor is basically adopted. This conventional method is efficient and has a large starting torque, but it generates about 5 ~ 6 times of inrush current at startup. As a result, the freezer starting device and peripheral devices are damaged and life time may be reduced. To reduce the inrush current, the current control algorithm based on the virtual dq model is presented to control the starting current. In addition, it validates the proposed algorithm through experiments to smooth transit from start-up operation to the rated operating region.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.15-24
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• 2000

The dielectric relaxation of high-dielectric capacitors could be understood as a dynamic property of the capacitor in the time domain, which is regarded as a primarily important charge loss mechanism during the refresh time of DRAMs. Therefore, the equivalent circuit of the dielectric relaxation of the high-dielectric capacitor is essentially required to investigate its effects on DRAM. Nevertheless, There is not any theoretical method which is generally applied to realize the equivalent circuit of the dielectric relaxation. Recently, we have developed a novel procedure for the circuit modeling of the dielectric relaxation of high-dielectric capacitor utilizing the frequency domain. This procedure is a general method based on theoretical approach. We have also verified the feasibility of this procedure through experimental process. Finally, we successfully investigated the effect of dielectric relaxation on DRAM operation with the obtained equivalent circuit through this new method.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.1
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• pp.71-80
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• 2015

LDO(Low Drop-Out) regulators have become an essential building block in modern PMIC(Power Managment IC) to extend battery life of electronic devices. In this paper, we optimize capacitor-less LDO regulator via Geometric Programming(GP) designed using Dongbu HiTek $0.5{\mu}m$ BCDMOS process. GP-compatible models for stability and PSR of LDO regulators are derived based on monomial formulation of transistor characteristics. Average errors between simulation and the proposed model are 9.3 % and 13.1 %, for phase margin and PSR, respectively. Based on the proposed models, the capacitor-less LDO optimization can be performed by changing the PSR constraint of the design. The GP-compatible performance models developed in this work enables the design automation of capacitor-less LDO regulator for different design target specification.