• Applied Chemistry for Engineering
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• v.34 no.4
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• pp.426-433
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• 2023

Capacitor performance was considered using coffee grounds-based activated carbon produced through oil extraction and KOH activation to increase the utilization of boiwaste. Oil extraction from coffee grounds was performed by solvent extraction using n-Hexane and isopropyl alcohol solvents. The AC_CG-Hexane/IPA produced by KOH activation after oil extraction increased the specific surface area by up to 16% and the average pore size by up to 2.54 nm compared to AC_CG produced only by KOH activation without oil extraction. In addition, the pyrrolic/pyridinic N functional group of the prepared activated carbon increased with the extraction of oil from coffee grounds. In the cyclic voltage-current method measurement experiment, the specific capacitance of AC_CG-Hexane/IPA at a voltage scanning speed of 10 mV/s is 133 F/g, which is 33% improved compared to the amorphous capacity of AC_CG (100 F/g). The results show improved electrochemical properties by improving the size and specific surface area of the mesopores of activated carbon by removing components from coffee grounds oil and synergistic effects by increasing electrical conductivity with pyrrolic/pyridinic N functional groups. In this study, the recycling method and application of coffee grounds, a bio-waste, is presented, and it is considered to be one of the efficient methods that can be utilized as an electrode material for high-performance supercapacitors.

• Journal of international Conference on Electrical Machines and Systems
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• v.2 no.4
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• pp.441-446
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• 2013

A thermal model of power modules based on the physical dimension and thermal properties is proposed in this paper. The heat path in the power module is considered as a one-dimensional heat transfer in the model. The method of the parameters extraction for the model is given in the paper. With high speed and accuracy, the thermal model is suit for electrothermal simulation. The proposed model is verified by experimental results.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.2 no.2
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• pp.30-37
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• 1991

The modified method which determines the extrinsic parameters at the small signal equivalent model for GaAs MESFET is presented. It is important that extrinsic parameters are completely eliminated, in order to calculate exact intrinsic parameters. Extrinsic circuit is established by transmission lines, parasitic inductors and capacitors. After these are extracted by S-parameters, intrinsic parameters are calculated. Especially, frequency dependence of parastic inductance and capacitance is considerally constant.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1525-1527
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• 1987

This paper describe the KUIC-CEX, an automated CMOS layout verification program which extracts circuit connectivity, MOSFET dimensions, and parasitic capacitance for CIF(1) file. In the KUIC-CEX, Bitmap approach(2, 3) is used for basic operation. Since the output of this program is the Input file format of PSPICE, we can easily verify the layout of circuit. This program is written in C language.

• Journal of the Korea Institute of Military Science and Technology
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• v.3 no.1
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• pp.155-163
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• 2000

A general characterization procedure based on the extraction of a 2n-port admittance matrix corresponding to n uniform coupled lines on the multi-layered substrate using the Finite-Difference Time-Domain (FDTD) technique is presented. The frequency-dependent normal mode parameters are obtained from the 2n-port admittance matrix, which in turn provides the frequency-dependent distributed inductance and capacitance matrices. To illustrate the technique, several practical coupled line structures on multi-layered substrate, including a three-line structure, have been simulated. It is shown that the FDTD based time domain characterization procedure is an excellent broadband simulation tool for the design of multiconductor coupled lines on multilayered PCBs as well as thick or thin hybrid structures.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.164-171
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• 1996

We report the experimental resutls on AlGaAs/GaAs heterojunction bipolar transistors (HBTs) with carbon-doped base structure. To characterize the output power, load-pull mehtod was employed. By characterizing the devices with HP8510C, we extracted the small-signal equivalent circuit. The HBTs were fabricated employing wet mesa etching and lift-off process of ohmic metals. the implementation of polyimide into the fabriction process was accomplished to obtain the lower dielectric constant resultig in significant reduction of interconnect routing capacitance. The fabricated HBTs with an emitter area of 6${\times}14{\mu}m^{2}$ exhibited current gain of 45, BV$_{CEO}$ of 10V, cut-off frequency of 30GHz and power gain of 1 3dBm. To extract the small signal equivalent circuit, the de-embedded method was applied for parasitic parameters and the calculation of circuit equations for intrinsic parameters.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.1
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• pp.52-59
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• 1991

An effective and accurate delay time model is the key problem in the simulation and timing verification of CMOS logic circuits. We propose a semi-analytic CMOW delay time model taking into account the configuration ratio, the input waveform slope and the load capacitance. This model is based on the Schichman Hodges's DC equations and derived on the optimally weighted switching peak current. The parameters necessary for the model calculation are automatically determined from the program. The proposed model is computationally effective and the error is typically within 10% of the SPICEA results. Compared to the table RC model, the accuracy is inproved over two times in average.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.2213-2215
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• 2000

In this paper we implemented a novel re-entrant mode microstrip directional coupler for realizing the high directivity characteristic using finite element (FE) analysis. In microstrip configuration, the high directivity can be reached by matching the even- and odd-mode effective phase velocities. Through the values of capacitance obtained from 2-dimensional finite element(FE) analysis, the phase velocities for each mode and the design parameter were extracted for the proposed coupled-line configuration. Based on the extracted design parameter with phase matching condition we designed and fabricated 30dB directional coupler at 850MHz. Experimental results show good performance with excellent isolation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.5
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• pp.347-352
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• 1998

In this paper, the extraction and optimization of SPICE parameters on SONOSFET for NVSM circuit design were discussed. SONOSFET devices with different channel widths and lengths were fabricated using conventional 1.2 um n-well CMOS process. And, electric properties for dc parameters and capacitance parameters were measured on wafer. SPICE parameters for the SONOSFET were extracted from the UC Berkeley level 3 model for the MOSFET. And, local optimization of Ids-Vgs curves has carried out in the bias region of subthreshold, linear, saturation respectively. Finally, the extracted SPICE parameters were optimized globally by comparing drain current (Ids), output conductance(gds), transconductance(gm) curves with theoretical curves in whole region of bias conditions. It is shown that the conventional model for the MOSFET can be applied to the SONOSFET modeling except sidewalk effect.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.27-34
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• 2004

The study on the RF substrate circuit is necessary to model RF output characteristics of deep submicron MOSFETs below 0.2$\mum$ gate length that have bun commercialized by the recent development of Si submicron process. In this paper, direct extraction methods are developed to apply for a simple substrate resistance model as well as another substrate model with connecting resistance and capacitance in parallel. Using these extraction methods, better agreement with measured Y22-parameter up to 30 GHz is achieved for 0.15$\mum$ CMOS device by using the parallel RC substrate model rather than the simple resistance one, demonstrating the RF accuracy of the parallel model and extraction technique. Using this model, bias and gate length dependent curves of substrate parameters in the RF region are obtained by increasing drain voltage of 0 to 1.2V at deep submicron devices with various gate lengths of 0.11 to 0.5㎛ These new extraction data will greatly contribute to developing a scalable RF nonlinear substrate model.