• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.12
• /
• pp.56-65
• /
• 2001

This paper proposes an algorithm for the capacitance extraction of general 3-dimensional conductors in an ideal uniform dielectric that uses a high-order quadrature approximation method combined with the typical first-order collocation method to enhance the accuracy and adopts an efficient matrix-vector product algorithm for the model-order reduction to achieve efficiency. The proposed method enhances the accuracy using the quadrature method for interconnects containing corners and vias that concentrate the charge density. It also achieves the efficiency by reducing the model order using the fact that large parts of system matrices are of numerically low rank. This technique combines an SVD-based algorithm for the compression of rank-deficient matrices and Gram-Schmidt algorithm of a Krylov-subspace iterative technique for the rapid multiplication of matrices. It is shown through the performance evaluation procedure that the combination of these two techniques leads to a more efficient algorithm than Gaussian elimination or other standard iterative schemes within a given error tolerance.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.14 no.1
• /
• pp.1-6
• /
• 2000

In this paper, organic dispersion type back light EL(Electroluminescent) devices were manufactured using Ethyl hydroxy ethyl cellulose as organic binder, ZnS:Cu as phosphor powder and $BaTiO_3$ as dielectrics by screen printing method, which are focused on as a new light source. The properties of the fabricated organic dispersion type back light EL devices were showed $1.98[mA/\m^2]$ of current density, 0.075[W] of power consumption, 7.1[nF] of capacitance at $25[^{\circ}C]$, 100[V], 400[Hz], respectively. Also brightness of the fabricated device was revealed $20~110[cd/\m^2]$ at 50~150[V] and the change of color was shoed bluish green of x=0.1711, y=0.3676 which are color coordinate by CIE.

• Korean Journal of Materials Research
• /
• v.26 no.8
• /
• pp.430-437
• /
• 2016

Aluminum oxide ($Al_2O_3$) thin films were grown by atomic layer deposition (ALD) using a new Al metalorganic precursor, dimethyl aluminum sec-butoxide ($C_{12}H_{30}Al_2O_2$), and water vapor ($H_2O$) as the reactant at deposition temperatures ranging from 150 to $300^{\circ}C$. The ALD process showed typical self-limited film growth with precursor and reactant pulsing time at $250^{\circ}C$; the growth rate was 0.095 nm/cycle, with no incubation cycle. This is relatively lower and more controllable than the growth rate in the typical $ALD-Al_2O_3$ process, which uses trimethyl aluminum (TMA) and shows a growth rate of 0.11 nm/cycle. The as-deposited $ALD-Al_2O_3$ film was amorphous; X-ray diffraction and transmission electron microscopy confirmed that its amorphous state was maintained even after annealing at $1000^{\circ}C$. The refractive index of the $ALD-Al_2O_3$ films ranged from 1.45 to 1.67; these values were dependent on the deposition temperature. X-ray photoelectron spectroscopy showed that the $ALD-Al_2O_3$ films deposited at $250^{\circ}C$ were stoichiometric, with no carbon impurity. The step coverage of the $ALD-Al_2O_3$ film was perfect, at approximately 100%, at the dual trench structure, with an aspect ratio of approximately 6.3 (top opening size of 40 nm). With capacitance-voltage measurements of the $Al/ALD-Al_2O_3/p-Si$ structure, the dielectric constant of the $ALD-Al_2O_3$ films deposited at $250^{\circ}C$ was determined to be ~8.1, with a leakage current density on the order of $10^{-8}A/cm^2$ at 1 V.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.344-344
• /
• 2013

칩의 크기가 감소함에 따라 RC (Resistance, Capacitance) 지연, 전력소비증가 및 신호잡음 등이 문제가 되어왔다. RC지연 문제는 배선에 알루미늄 보다 비저항이 낮은 구리를 사용하고 절연막으로 유전상수가 낮은 물질을 사용하여 개선될 수 있다. 이와 같은 맥락에서 점차 저유전상수 박막의 필요성은 증가하고 있다. 그러므로 이를 개선하기 위해 저 유전상수 값을 가지는 물질을 개발 혹은, UV나 플라즈마 그리고 열을 이용하여 처리하는 연구가 절실히 요구되고 있으며, 현재 많은 연구가 진행되고 있다. 이 논문에서 저유전박막은 HDP-CVD (High Density Plasma Chemical Vapor Deposition) 시스템에서 (CyOz)-SiHx와 O2의 비율을 각각 변화시키면서 증착 되었다. (CyOz)-SiHx와 O2의 비율은 60/150, 60/180, 60/210, 60/240로 증가하면서 증착하였다. 그리고 surface profilometer을 이용하여 박막의 증착율을 측정하고 LCR meter를 이용하여 정전용량을 측정하여 유전상수 값을 얻었다. 박막의 화학적 조성과 구조는 FTIR (Fourier Transform Infrared Spectroscopy)로 측정하였다. 박막의 유동 특성은 SEM (Scanning electron microscope) 이미지로 살펴보았다.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.66 no.5
• /
• pp.800-805
• /
• 2017

The accelerated thermal ageing of CSPE (chlorosulfonated polyethylene) was carried out for 16.82, 50.45, and 84.09 days at $110^{\circ}C$, equivalent to 20, 60, and 100 years of ageing at $50^{\circ}C$ in nuclear power plants, respectively. As the accelerated thermally aged years increase, the insulation resistance and resistivity of the CSPE decrease, and the capacitance, relative permittivity and dissipation factor of those increase at the measured frequency, respectively. As the accelerated thermally aged years and the measured frequency increase, the phase degree of response voltage vs excitation voltage of the CSPE increase but the phase degree of response current vs excitation voltage decrease, respectively. As the accelerated thermally aged years increase, the apparent density, glass transition temperature and the melting temperature of the CSPE increase but the percent elongation and % crystallinity decrease, respectively. The differential temperatures of those are $0.013-0.037^{\circ}C$ and, $0.034-0.061^{\circ}C$ after the AC and DC voltages are applied to CSPE-0y and CSPE-20y, respectively; the differential temperatures of those are $0.011-0.038^{\circ}C$ and $0.002-0.028^{\circ}C$ after the AC and DC voltages are applied to CSPE-60y and CSPE-100y, respectively. The variations in temperature for the AC voltage are higher than those for the DC voltage when an AC voltage is applied to CSPE. It is found that the dielectric loss owing to the dissipation factor($tan{\delta}$) is related to the electric dipole conduction current. It is ascertained that the ionic (electron or hole) leakage current is increased by the partial separation of the branch chain of CSPE polymer as a result of thermal stress due to accelerated thermal ageing.

• Journal of Powder Materials
• /
• v.18 no.2
• /
• pp.149-158
• /
• 2011

Electro-Discharge Sintering (EDS) employs a high-voltage/high-current-density pulse of electrical energy, discharged from a capacitor bank, to instantaneously consolidate powders. In the present study, a single pulse of 0.57-1.1 kJ/0.45 g-atomized spherical $Ti_{52}Zr_{28}Ni_{20}$ powders in size range of 10~30 and $30\sim50{\mu}m$ consisting of ${\beta}$-(Ti, Zr) and icosahedral phases were applied to examine the structural evolution of icosahedral phase during EDS. Structural investigation reveals that high electrical input energy facilitates complete decomposition of icosahedral phase into C14 laves and ${\beta}$-(Ti, Zr) phases. Moreover, critical input energy inducing decomposition of the icosahedral phase during EDS depends on the size of the powder. Porous Ti and W compacts have been fabricated by EDS using rectangular and spherical powders upon various input energy at a constant capacitance of $450{\mu}F$ in order to verify influence of powder shape on microstructure of porous compacts. Besides, generated heat (${\Delta}H$) during EDS, which is measured by an oscilloscope, is closely correlated with powder size.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.5
• /
• pp.664-674
• /
• 2016

The electrical properties of Ti/p-type InP Schottky diodes with and without polyaniline (PANI) interlayer was investigated using current-voltage (I-V) and capacitance-voltage (C-V) measurements. The barrier height of Ti/p-type InP Schottky diode with PANI interlayer was higher than that of the conventional Ti/p-type InP Schottky diode, implying that the organic interlayer influenced the space-charge region of the Ti/p-type InP Schottky junction. At higher voltages, the current transport was dominated by the trap free space-charge-limited current and trap-filled space-charge-limited current in Ti/p-type InP Schottky diode without and with PANI interlayer, respectively. The domination of trap filled space-charge-limited current in Ti/p-type InP Schottky diode with PANI interlayer could be associated with the traps originated from structural defects prevailing in organic PANI interlayer.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.8 s.338
• /
• pp.53-60
• /
• 2005

Recently, sub-micron CMOS technologies have taken the place of III-V materials in a number of areas in integrated circuit designs, in particular even for the applications of gjgabit optical communication applications due to its low cost, high integration level, low power dissipation, and short turn-around time characteristics. In this paper, a four-channel transimpedance amplifier (TIA) array is realized in a standard 0.35mm CMOS technology Each channel includes an optical PIN photodiode and a TIA incorporating the fully differential regulated cascode (RGC) input configuration to achieve effectively enhanced transconductance(gm) and also exploiting the inductive peaking technique to extend the bandwidth. Post-layout simulations show that each TIA demonstrates the mid-band transimpedance gain of 59.3dBW, the -3dB bandwidth of 2.45GHz for 0.5pF photodiode capacitance, and the average noise current spectral density of 18.4pA/sqrt(Hz). The TIA array dissipates 92mw p in total from a single 3.3V supply The four-channel RGC TIA array is suitable for low-power, high-speed optical interconnect applications.

• Composites Research
• /
• v.29 no.4
• /
• pp.179-185
• /
• 2016

A self-charging supercapacitor is constructed through simple integration of the energy storage and photo exited materials at the photo electrode. The large band gap of $NiO/Fe_3O_4$ heterostructure generates photo electron at the photo electrode and store the charges through redox mechanism at the counter electrode. Sulfanilic acid azocromotrop/reduced graphene oxide layer at the photo electrode trapped the photo generated hole and store the charge by forming double layer. The solar supercapacitor device is charged within 400 s up to 0.5 V and exhibited a high specific capacitance of ~908 F/g against 1.5 A/g load. The solar illuminated supercapacitor shows a high energy and power density of 33.4 Wh/kg and 385 W/kg along with a very low relaxation time of ~15 ms ensuring the utility of the self charging device in the various field of energy storage and optoelectronic application.

• Journal of the Korean Vacuum Society
• /
• v.11 no.3
• /
• pp.135-140
• /
• 2002

In this paper, We deposited the BST thin-film on p-type (100)Si, (100)MgO and MgO/Si substrates respectively using RF magnetron sputtering method. After the BST thin-fil m was deposited, we performed RTA(rapid thermal anneal) at $600^{\circ}C$, oxygen atmosphere and 1 min. In the XRD measurement, we observed the (110) $Ba_{0.5}Sr_{0.5}TiO_3$ main peak in all samples and the peak intensity increased after post annealing. Then we manufactured a capacitor using Al Electrode and measured I-V, C-V. In C-V measurement result values for each substrate, dielectric constant was calculated 120 (bare Si), 305(MgO/Si), 310(MgO) respectively. A leakage current density was present less than 1 $\mu\textrm{A/cm}^2$ at applied fields below 0.3 MV/cm. In conclusion we confirmed that MgO/Si substrates give good results for BST thin-film deposition.