• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.140-140
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• 2009

The Metal-ferroelectric-semiconductor (MFS) structure has superior advantages such as high density integration and non-destructive read-out operation. However, to obtain the desired electrical characteristics of an MFS structure is difficult because of interfacial reactions between ferroelectric thin film and Si substrate. As an alternative solution, the MFS structure with buffer insulating layer, i.e. metal-ferroelectric-insulator-semiconductor (MFIS), has been proposed to improve the interfacial properties. Insulators investigated as a buffer insulator in a MFIS structure, include $Ta_2O_5$, $HfO_2$, and $ZrO_2$ which are mainly high-k dielectrics. In this study, we prepared the Dy-doped $La_2O_3$ solution buffer layer as an insulator. To form a Dy-doped $La_2O_3$ buffer layer, the solution was spin-coated on p-type Si(100) wafer. The coated Dy-doped $La_2O_3$ films were annealed at various temperatures by rapid thermal annealing (RTA). To evaluate electrical properties, Au electrodes were thermally evaporated onto the surface of the samples. Finally, we observed the surface morphology and crystallization quality of the Dy-doped $La_2O_3$ on Si using atomic force microscopy (AFM) and x-ray diffractometer (XRD), respectively. To evaluate electrical properties, the capacitance-voltage (C-V) and current density-voltage (J-V) characteristics of Au/Dy-doped La2O3/Si structure were measured.

• 한국정보통신학회논문지
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• 제15권6호
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• pp.1349-1354
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• 2011

본 연구에서는 CdZnS와 CdTe로 구성되는 이종접합 소자를 제작하고 커패시턴스-전압 특성을 조사하였다. CdS/CdTe 접합의 경우, 역방향 바이어스가 증가함에 따라 공핍층의 폭이 커져 커패시턴스 값이 약간 감소하였으나 CdZnS/CdTe 접합에서는 CdTe 박막 내에서의 공핍층 폭이 바이어스에 크게 영향을 받지 않아 커패시턴스 값이 역방향 바이어스에 따라 거의 변화가 없었다. 바이어스 전압을 인가하지 않은 상태에서의 공핍층 폭은 높은 CdZnS 박막의 비저항 및 낮은 캐리어 농도로 인해 CdS/CdTe 접합보다 CdZnS/CdTe 접합에서 보다 큰 값을 나타내었다. CdZnS/CdTe 태양전지의 개방전압은 Zn의 비율이 커짐에 따라 CdZnS 박막과 CdTe 박막의 전자 친화력 차이의 감소로 인하여 크게 증가하였으나, Zn 비율이 0.35 이상인 경우 오히려 감소함을 알 수 있었다. 또한 CdZnS 박막의 높은 비저항이 태양전지의 직렬저항을 상승시켜 전지의 변환 효율은 오히려 감소함을 알 수 있었다.

• 한국재료학회지
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• 제20권7호
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• pp.374-378
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• 2010

$MgTiO_3$ thin films were prepared by r.f. magnetron sputtering in order to prepare miniaturized NPO type MLCCs. $MgTiO_3$ films showed a polycrystalline structure of ilmenite characterized by the appearance of (110) and (202) peaks. The intensity of the peaks decreased with an increase in the chamber pressure due to the decrease of crystallinity which resulted from the decrease of kinetic energy of the sputtered atoms. The films annealed at $600^{\circ}C$ for 60min. showed a fine grained microstructure without micro-cracks. The grain size and roughness of the $MgTiO_3$ films decreased with the increase of chamber pressure. The average surface roughness was 1.425~0.313 nm for $MgTiO_3$ films prepared at 10~70 mTorr. $MgTiO_3$ films showed a dielectric constant of 17~19.7 and a dissipation factor of 2.1~4.9% at 1MHz. The dielectric constant of the films is similar to that of bulk ceramics. The dielectric constant and the dissipation factor decreased with the increase of the chamber pressure due to the decrease of grain size and crystallinity. The leakage current density was $10^{-5}\sim10^{-7}A/cm^2$ at 200kV/cm and this value decreased with the increase of the chamber pressure. The small grain size and smooth surface microstructure of the films deposited at high chamber pressure resulted in a low leakage current density. $MgTiO_3$ films showed a near zero temperature coefficient and satisfied the specifications for NPO type materials. The dielectric properties of the $MgTiO_3$ thin films prepared by sputtering suggest the feasibility of their application for MLCCs.

• 전자공학회논문지
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• 제52권8호
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• pp.59-63
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• 2015

본 연구에서는 MONOS 플래시 메모리의 blocking oxide/trapping nitride, trapping nitride/tunneling oxide 계면 트랩을 구하기 위해 C-V 방법을 도입하였고, stoichiometric 조건을 만족하는 nitride와 silicon rich nitride를 trapping layer로 갖는 MONOS capacitor를 제작하여 각각의 interface trap 특성을 비교분석하였다. 보고에 따르면 silicon rich nitride는 stoichiometric nitride에 비해 다수의 shallow trap이 존재한다고 보고되고 있는데, 본 연구를 통해 이의 정량화가 가능함을 보였다.

• 전기전자학회논문지
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• 제18권4호
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• pp.620-624
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• 2014

본 연구에서는, Ni/CNT/$SiO_2$ 구조의 4H-SiC MIS 캐패시터를 제작하고 전기적 특성을 조사하였다. 이를 통하여 4H-SiC MIS 소자에서 탄소나노튜브의 역할을 분석하고자 하였다. 탄소나노튜브는 이소프로필알코올과 혼합하여 $SiO_2$ 표면에 분산하였다. 소자의 전기적 특성 분석을 위하여 300-500K의 온도 범위에서 소자의 정전용량-전압 특성을 측정하였다. 밴드 평탄화 전압은 양의 방향으로 shift되었다. 정전용량-전압 그래프로부터 계면 포획 전하 밀도 및 산화막 포획 전하 밀도가 유도되었다. 산화막의 상태는 4H-SiC MIS 구조의 계면에서 전하 반송자 또는 결함 상태와 관련된다. 온도가 증가함에 따라 밴드 평탄화 전압은 음의 방향으로 shift되는 결과를 얻었다. 실험 결과로부터, Ni과 $SiO_2$ 계면에 탄소나노튜브를 첨가함에 따라 4H-SiC MIS 캐패시터의 게이트 특성을 조절 가능할 것으로 판단된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 유기절연재료 전자세라믹 방전플라즈마 일렉트렛트 및 응용기술
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• pp.47-52
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• 2002

A processing method is developed for preparing sol-gel derived $Pb(Zr_{1-x}Ti_x)O_3$ (x=0.5) thin films on Pt-Ir($Pt_{80}Ir_{20}$)-alloy substrates. The as-deposited layer was dried on a plate in air at $70^{\circ}C$. And then it was baked at $1500^{\circ}C$, annealed at $450^{\circ}C$ and finally annealed for crystallization at various temperatures ranging from $580^{\circ}C$ to $700^{\circ}C$ for 1hour in a tube furnace. The thickness of the annealed film with three layers was $0.3{\mu}m$. Crystalline properties and surface morphology were examined using X-ray diffractometer (XRD). Electrical properties of the films such as dielectric constant, C-V, leakage current density were measured under different annealing temperature. The PZT thin film which was crystallized at $600^{\circ}C$ for 60minutes showed the best structural and electrical dielectric constant is 577. C-V measurement show that $700^{\circ}C$ sample has window memory volt of 2.5V and good capacitance for bias volts. Leakage current density of every sample show $10^{-8}A/cm^2$ r below and breakdown voltage(Vb) is that 25volts.

• 한국재료학회지
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• 제27권4호
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• pp.192-198
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• 2017

Carbon nanofiber (CNF) is used as an electrode material for electrical double layer capacitors (EDLCs), and is being consistently researched to improve its electrochemical performance. However, CNF still faces important challenges due to the low mesopore volume, leading to a poor high-rate performance. In the present study, we prepared the unique architecture of the activated mesoporous CNF with a high specific surface area and high mesopore volume, which were successfully synthesized using PMMA as a pore-forming agent and the KOH activation. The activated mesoporous CNF was found to exhibit the high specific surface area of $703m^2g^{-1}$, total pore volume of $0.51cm^3g^{-1}$, average pore diameter of 2.9 nm, and high mesopore volume of 35.2 %. The activated mesoporous CNF also indicated the high specific capacitance of $143F\;g^{-1}$, high-rate performance, high energy density of $17.9-13.0W\;h\;kg^{-1}$, and excellent cycling stability. Therefore, this unique architecture with a high specific surface area and high mesopore volume provides profitable synergistic effects in terms of the increased electrical double-layer area and favorable ion diffusion at a high current density. Consequently, the activated mesoporous CNF is a promising candidate as an electrode material for high-performance EDLCs.

• 한국결정성장학회지
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• 제24권1호
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• pp.41-45
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• 2014

다양한 공정 조건으로 $SiN_x$와 $SiO_2$ 박막을 형성하고 이에 대한 패시베이션 특성에 대한 연구를 수행하였다. Plasma enhanced chemical vapor deposition(PECVD)을 이용하여 증착된 $SiN_x$ 박막의 경우, 증착 두께가 증가함에 따라 페시베이션 특성이 향상되는 것을 관찰하였다. 이는 PECVD 증착 공정 중 유입되는 수소 원자들이 실리콘 표면에 존재하는 Dangling bond와 결합하여 소수 캐리어의 재결합 현상을 효과적으로 감소시켰기 때문이다. 건식 산화법으로 형성된 $SiO_2$ 박막은 습식 산화법으로 형성된 것 보다 치밀한 계면 구조를 가짐으로 인하여 약 20배 이상 우수한 패시베이션 특성을 나타내었다. 건식 산화 공정 온도가 증가함에 따라 패시베이션 특성이 열화되는 현상이 발생하였고, Capacitance-voltage(C-V) 및 Conductance-voltage(G-V) 분석을 통하여 $SiO_2$/실리콘 계면에 존재하는 계면 결함 밀도 증가에 의해 나타나는 현상임을 알 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.49-49
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• 2008

ZnO-based varistors have been widely used for voltage stabilization or transient surge suppression in electric power systems and electronic circuits. Recently, It has reported that the varistor behavior with nonlinear coefficient of 6~17 in Mn-doped ZnO. In this study we have chosen the composition of ZnO-$TeO_2-Mn_3O_4$ (ZTM) system to the purpose of whether varistor behavior appeared in doped ZnO by the solid state sintering or not. We investigated the sintering and electric properties of 0.5~3.0 at% Mn doped ZnO-1.0 at% $TeO_2$ system. Electrical properties, such as current-voltage (I-V), capacitance-voltage (C-V), and impedance spectroscopy were conducted. $TeO_2$ itself melts at $732^{\circ}C$ in air but forms the $ZnTeO_3$ phase with ZnO as increasing temperature and therefore retards the densification of ZnO to $1000^{\circ}C$. The average grain size of sintered samples was at about $3{\mu}m$ and decreased with increasing Mn contents. It was found that a good varistor characteristics were developed in ZTM system sintered at $1100^{\circ}C$ (nonlinear coefficient $\alpha$ ~ 60). The results of C-V characteristics such as barrier height ($\Theta$), donor density ($N_d$), depletion layer (W), and interface state density ($N_t$) in ZTM ceramics were $4\times10^{17}cm^{-3}$, 0.7 V, 40 nm, and $1.6\times10^{12}cm^{-2}$, respectively. It will be discussed about the stability and homogeneity of grain boundaries using distribution parameter ($\alpha$) simulated with the Z(T)"-logf plots in ZTM system.

• 전기학회논문지
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• 제66권2호
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• pp.357-362
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• 2017

Among the lithium metal oxides for asymmetric hybrid supercapacitor, $Li_4Ti_5O_{12}(LTO)$ is an emerging electrode material as zero-stain material in volume change during the with the charging and discharging processes. The pulverized LTO powder was observed to show the enhanced capacity from 120 mAh/g to 156 mAh/g at C-rate (10, 100 C). Hybrid supercapacitor module(48V, 416F) was fabricated using an asymmetric hybrid capacitor with a capacitance of 7500F. As a result of the measurement of C-rate characteristics, the module shows that the discharge time is drastically reduced at more than 50C, and the ESR and voltage drop characteristics are increased. The energy density and power density were reduced under high C-rate conditions. When designing asymmetric hybrid supercapacitor module, the C-rate and ESR should be considered As a result of measuring the 5 kw UPS, it was discharged at the current of 116A~170A during the discharge in the voltage range of 48V~30V, and the compensation time at discharge was measured to be about 33.2s. Experimental results show that it can be applied to applications related to stabilization of power quality by applying hybrid supercapacitor module.