• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2375-2381
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• 2014

In case the coefficient set of an FIR filter is represented in the canonic signed digit (CSD) format with a few nonzero digits, it is possible to implement high data rate digital filters with low hardware cost. Designing an FIR filter with CSD format coefficients, whose number of nonzero signed digits is minimal, is equivalent to finding sparse nonzero signed digits in the coefficient set of the filter which satisfies the target frequency response with minimal maximum error. In this paper, a compressive sensing based CSD coefficient FIR filter design algorithm is proposed for multiplierless and high speed implementation. Design examples show that multiplierless FIR filters can be designed using less than two additions per tap on average with approximate frequency response to the target, which are suitable for high speed filtering applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.2
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• pp.31-38
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• 2012

In this paper, a low area timing synchronization structure for the IEEE 802.11a OFDM MODEM SoC is proposed. The timing synchronization block of the IEEE 802.11a OFDM MODEM SoC requires large implementation area. In the proposed timing synchronization structure, it is shown that the number of multiplication can be reduced by using the transposed direct form filter. Furthermore, implementation area of the proposed structure can be more reduced using CSD(Canonic Signed Digit) and Common Sub-expression Sharing techniques. Through Verilog-HDL coding and synthesis, it is shown that the 22.7 % of implementation area can be reduced compared with the conventional one.

• Journal of IKEEE
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• v.19 no.3
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• pp.342-348
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• 2015

High speed implementation of digital filters is required in high data rate applications such as hard-wired wide band modem and high resolution video codec. Since the critical path of the digital filter is the MAC (multiplication and accumulation) circuit, the filter coefficient with sparse non-zero bits enables high speed implementation with adders of low hardware cost. Compressive sensing has been reported to be very successful in sparse representation and sparse signal recovery. In this paper a filter design method for digital FIR filters with CSD (canonic signed digit) coefficients using compressive sensing technique is proposed. The sparse non-zero signed bits are selected in the greedy fashion while pruning the mistakenly selected digits. A few design examples show that the proposed method can be utilized for designing sparse CSD coefficient digital FIR filters approximating the desired frequency response.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.3
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• pp.1387-1394
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• 2011

In this paper, a low-area symbol timing offset synchronization structure for WLAN Modem is proposed. Using CSD(Canonic Signed Digit) coefficients and CSS(Common Sub-expression Sharing) technique for the filter implementation, efficient structure for multiplication block can be obtained. Function simulation for proposed structure is done by using the preamble with timing offset. Through Verilog-HDL coding and synthesis, it is shown that the proposed symbol timing offset synchronization structure can be implemented with low-area semiconductor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.119-128
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• 2004

In this paper, a low-power 8-point DCT structure is proposed using add and shift operations. Proposed structure adopts 4 cycles for complete 8-point DCT in order to minimize size of hardware and to enable high-speed processing. In the structure, hardware for the first cycle can be shared in the next 3 cycles since all columns in the DCT coefficient matrix are common except sign. Conventional DCT structures implemented with only add and shift operation use CSD(Canonic Signed Digit) form coefficients to reduce the number of adders. To reduce the number of adders further, we propose a new structure using common sub-expression sharing techniques. With this techniques, the proposed 8-point DCT structure achieves 19.5% adder reduction comparison to the conventional structure using only CSD coefficient form.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.5
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• pp.283-290
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• 2004

In this paper, a low-power structure for 512 tap FIR filter in MPEG audio algorithm is proposed. By using CSD(Canonic Signed Digit) form filter coefficients and maximum sharing of input signal sample, it is shown that the number of adders of proposed structure can be minimized. To minimize the number of adders, the proposed structure utilizes the 4 steps of sharing, i.e., common input sharing, linear phase symmetric filter coefficient sharing, block sharing for common input, and common sub-expression sharing. Through Verilog-HDL coding, it is shown that reduction rates in the implementation area and relative power consumption of the proposed structure are 60.3% and 93.9% respectively, comparison to those of the conventional multiplier structure.

• Journal of Biomedical Engineering Research
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• v.28 no.3
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• pp.423-428
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• 2007

Programmable FIR filters are used in various signal processing tasks in medical ultrasound imaging, which are one of the major factors increasing hardware complexity. A widely used method to reduce the hardware complexity of a programmable FIR filter is to encode the filter coefficients in the canonic signed digit (CSD) format to minimize the number of nonzero digits (NZD) so that the multipliers for each filter coefficients can be replaced with fixed shifters and programmable multiplexers (PM). In this paper, a new structure for programmable FIR filters with a improved frequency response and a reduced hardware complexity compared to the conventional shift-and-add architecture using PM is proposed for implementing a very small portable ultrasound scanner. The CSD codes are optimized such that there exists at least one common nonzero digit between neighboring coefficients. Such common digits are then implemented with the same shifters. For comparison, synthesisable VHDL models for programmable FIR filters are developed based on the proposed and the conventional architectures. When these filters have the same hardware complexity, pass-band ana stop-band ripples of the proposed filter are lower than those of the conventional filter by about $0.01{\sim}0.19dB$ and by about $5{\sim}10dB$, respectively. For the same filter performance, the hardware complexity of the proposed architecture is reduced by more than 20% compare to the conventional SaA architecture.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.236-239
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• 1999

This paper describes a low-power design of decimation filter. To reduce power consumption, an approximate processing method which controls the error in canonic signed digit(CSD) coefficients is proposed. The CSD representation reduces the number of operations by representing multiplications with add and shift operations. The proposed method further reduces the number of operations by controlling the error of CSD coefficient. Processor type architecture is used to implement the proposed method. Simulation result shows that the number of operations is reduced to 56%, 35% and 10% at each approximated filter level.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.1
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• pp.79-85
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• 2005

In this paper, low-power design and implementation techniques for IMT-2000 interpolation filter are proposed. Processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized for low-power implementation. proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of filter coefficient. Finally, in third shift register block, multiplied values are output and stored in shift register. For IMT-2000 interpolation filter, proposed and conventional structures are implemented by using Verilog-HDL coding. Gate counts for the proposed structure is reduced to 31.57% comparison with those of the conventional one.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.8-14
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• 2012

In this paper, a low-area FFT structure using $Radix-4^2$ algorithm is proposed. The large point FFT structure consists of cascade connection of the many stages. In implementation of large point FFT using $Radix-4^2$ algorithm, stages which number of different coefficients are only 3 appear in every 2 stages. For example, in the 4096-point FFT, the stages that number of different coefficients are 3 appear in stage 1, 3, and 5 among 6 stages. Multiplication block area of these 3 stages can be reduced using CSD(Canonic Signed Digit) and common sub-expression sharing techniques. Using the proposed structure, the 256-point FFT is implemented with the Verilog-HDL coding and synthesized by $1.971mm^2$ cell area in tsmc $0.18{\mu}m$CMOS library. This result shows 23% cell area reduction compared with the conventional structure.