• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.101-109
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• 2009

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.

• The KIPS Transactions:PartA
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• v.13A no.2 s.99
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• pp.123-136
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• 2006

The prefetching technique is an effective way to reduce the latency caused memory access. However, excessively aggressive prefetch not only leads to cache pollution so as to cancel out the benefits of prefetch but also increase bus traffic leading to overall performance degradation. In this thesis, a prefetch filtering scheme is proposed which dynamically decides whether to commence prefetching by referring a filtering table to reduce the cache pollution due to unnecessary prefetches In this thesis, First, prefetch hashing table 1bitSC filtering scheme(PHT1bSC) has been shown to analyze the lock problem of the conventional scheme, this scheme such as conventional scheme used to be N:1 mapping, but it has the two state to 1bit value of each entries. A complete block address table filtering scheme(CBAT) has been introduced to be used as a reference for the comparative study. A prefetch block address lookup table scheme(PBALT) has been proposed as the main idea of this paper which exhibits the most exact filtering performance. This scheme has a length of the table the same as the PHT1bSC scheme, the contents of each entry have the fields the same as CBAT scheme recently, never referenced data block address has been 1:1 mapping a entry of the filter table. On commonly used prefetch schemes and general benchmarks and multimedia programs simulates change cache parameters. The PBALT scheme compared with no filtering has shown enhanced the greatest 22%, the cache miss ratio has been decreased by 7.9% by virtue of enhanced filtering accuracy compared with conventional PHT2bSC. The MADT of the proposed PBALT scheme has been decreased by 6.1% compared with conventional schemes to reduce the total execution time.

• Journal of KIISE:Databases
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• v.34 no.5
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• pp.448-464
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• 2007

Location-Based Services (LBSs) provide results to queries according to the location of the client issuing the query. In LBS, techniques such as caching and prefetching are effective approaches to reducing the data transmission from a server and query response time. However, they can lead to cache inefficiency and network overload due to the client's mobility and query pattern. To solve these drawbacks, we propose a semantic prefetching (SP) scheme using prefetching segment concept and improved cache replacement policies. When a mobile client enters a new service area, called semantic prefetching area, proposed scheme fetches the necessary semantic information from the server in advance. The mobile client maintains the information in its own cache for query processing of location-dependent data (LDD) in mobile computing environment. The performance of the proposed scheme is investigated in relation to various environmental variables, such as the mobility and query pattern of user, the distributions of LDDs and applied cache replacement strategies. Simulation results show that the proposed scheme is more efficient than the well-known existing scheme for range query and nearest neighbor query. In addition, applying the two queries dynamically to query processing improves the performance of the proposed scheme.

• The KIPS Transactions:PartD
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• v.10D no.4
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• pp.655-660
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• 2003

The cache used by mobile host is an important device that recovers the weak points of limited power and bandwidth, in mobile computing environments. However, it has to stand and maintain the consistency with the server data. In this paper, we propose a 'Selective Cache Consistency Scheme'. The server allows an effective broadcasting by selecting data of high usability using 'Cache State Table' and 'Data Access Table'. Moreover, this scheme prevents the loss of data that nay occur by a long period of disconnection, by asynchronous broadcasting and transmitting those broadcast data preserved in the server. This also allows user to possess the latest data. Through experiments, we have found that the enlargement of autonomy is possible by reducing the dependence of server.

• Journal of KIISE
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• v.44 no.8
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• pp.854-859
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• 2017

Caching popular videos in the storage of base stations is an efficient method to reduce the transmission latency. This paper proposes an incentive proactive cache mechanism in the wireless network to motivate the content providers (CPs) to participate in the caching procedure. The system consists of one/many Infrastructure Provider (InP) and many CPs. The InP aims to define the price it charges the CPs to maximize its revenue while the CPs compete to determine the number of files they cache at the InP's base stations (BSs). We conceive this system within the framework of Stackelberg game where InP is considered as the leader and CPs are the followers. By using backward induction, we show closed form of the amount of cache space that each CP renting on each base station and then solve the optimization problem to calculate the price that InP leases each CP. This is different from the existing works in that we consider the non-uniform pricing scheme. The numerical results show that InP's profit in the proposed scheme is higher than in the uniform pricing.

• Journal of KIISE
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• v.42 no.8
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• pp.947-953
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• 2015

PRAM is being considered as a potential successor to DRAM because of its characteristics such as byte-addressability, non-volatility, and high density. To gain its benefits, buffer cache replacement algorithm based on PRAM has been actively studied. However, most of the previous studies on buffer cache replacement algorithm limitedly exploit the byte-level performance of PRAM by focusing its limited lifetime and slower access latency compared to DRAM. In this paper, we propose a novel buffer cache replacement algorithm that fully considers the byte-level performance of PRAM and the performance of secondary storage. To take advantage of small size write on PRAM, proposed scheme keeps pages, which are frequently accessed with a small size write, on PRAM and allows the selective page migration from DRAM to PRAM. As a result, our scheme significantly reduces the number of PRAM writes. Our experimental results indicate for real workloads that our scheme reduces the number of PRAM writes by up to 92% and improves its performance by up to 62% compared to CLOCK.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.3
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• pp.873-889
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• 2014

IP address lookup is very crucial in performance of routers. Several works have been done on prefix caching to enhance the performance of IP address lookup. Since a prefix represents a range of IP addresses, a prefix cache shows better performance than an IP address cache. However, not every prefix is cacheable in itself. In a prefix cache it causes false hit to cache a non-leaf prefix because there is possibly the longer matching prefix in the routing table. Prefix expansion techniques such as complete prefix tree expansion (CPTE) make it possible to cache the non-leaf prefixes as the expanded forms, but it is hard to manage the expanded prefixes. The expanded prefixes sometimes incur a great deal of update overhead in a routing table. We propose a bitmap-based prefix cache (BMCache) to provide low update overhead as well as low cache miss ratio. The proposed scheme does not have any expanded prefixes in the routing table, but it can expand a non-leaf prefix using a bitmap on caching time. The trace-driven simulation shows that BMCache has very low miss ratio in spite of its low update overhead compared to other schemes.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.10 no.1
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• pp.95-105
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• 2006

The speed of hard disk which is based on mechanical operation is more slow than processor. The growth of processor speed is rapid by semiconductor technology, but the growth of disk speed which is based on mechanical operation is not enough. Buffer cache in main memory and disk cache in disk controller have been used in computer system to solve the speed gap between processor and I/O subsystem. In this paper, an efficient buffer cache and disk cache management scheme was proposed to restrict duplicated disk block between buffer cache and disk cache. The performance of the proposed algorithm was evaluated by simulation.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.10
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• pp.579-585
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• 2003

Recently most of 3D graphics rendering Processors have the pixel cache storing depth data and color data to reduce the memory latency and the bandwidth requirement. In this paper, we propose the effective pixel cache for improving the performance of a rendering processor. The proposed cache system stores the depth data selectively based on the result of Z-test and the color data are stored into the auxiliary buffer. Simulation results show that the 16Kbyte proposed cache system provides better performance than the 32Kbyte conventional cache.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.11
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• pp.5673-5691
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• 2019

Information centric mobile network can significantly improve the data retrieving efficiency by caching contents at mobile edge. However, the cache pollution attack can affect the data obtaining process severely by requiring unpopular contents deliberately. To tackle the problem, we design an algorithm of mitigating cache pollution attacks in information centric mobile network. Particularly, the content popularity distribution statistic is proposed to detect abnormal behavior. Then a probabilistic caching strategy based on abnormal behavior is applied to dynamically maintain the steady-state distribution for content visiting probability and achieve the purpose of defense. The experimental results show that the proposed scheme can achieve higher request hit ratio and smaller latency for false locality content pollution attack than the CacheShield approach and the baseline approach where no mitigation approach is applied.