• The Journal of the Korea Contents Association
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• v.14 no.11
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• pp.28-38
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• 2014

In this paper, we propose the distributed cache management scheme to efficiently access small files in Hadoop Distributed File Systems(HDFS). The proposed scheme can reduce the number of metadata managed by a name node since many small files are merged and stored in a chunk. It is also possible to reduce the file access costs, by keeping the information of requested files using the client cache and data node caches. The client cache keeps small files that a user requests and metadata. Each data node cache keeps the small files that are frequently requested by users. It is shown through performance evaluation that the proposed scheme significantly reduces the processing time over the existing scheme.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.11
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• pp.658-672
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• 2004

Multimedia applications are required to process the huge amount of data at high speed in real time. The memory reference instructions such as loads and stores are the main factor which limits the high speed execution of processor. To enhance the memory reference speed, cache prefetch schemes are used so as to reduce the cache miss ratio and the total execution time by previously fetching data into cache that is expected to be referenced in the future. In this study, we present an advanced data cache prefetching scheme that improves the conventional RPT (reference prediction table) based scheme. We considers the cache line size in calculation of the address stride referenced by the same instruction, and enhances the prefetching algorithm so that the effect of prefetching could be maintained even if an irregular address stride is inserted into the series of uniform strides. According to experiment results on multimedia benchmark programs, the cache miss ratio has been improved 29% in average compared to the conventional RPT scheme while the bus usage has increased relatively small amount (0.03%).

• Journal of KIISE
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• v.44 no.7
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• pp.658-667
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• 2017

The demand for large-scale storage systems has continued to grow due to the emergence of multimedia, social-network, and big-data services. In order to improve the response time and reduce the load of such large-scale storage systems, DRAM-based in-memory cache systems are becoming popular. However, the high cost of DRAM severely restricts their capacity. While the method of compressing cache entries has been proposed to deal with the capacity limitation issue, compression and decompression, which are technically difficult to parallelize, induce significant processing overhead and in turn retard the response time. A selective compression scheme is proposed in this paper for in-memory file system caches that rapidly estimates the compression ratio of incoming cache entries with their Shannon entropies and compresses cache entries with low compression ratio. In addition, a description is provided of the design and implementation of an in-kernel in-memory file system cache with the proposed selective compression scheme. The evaluation showed that the proposed scheme reduced the execution time of benchmarks by approximately 18% in comparison to the conventional non-compressing in-memory cache scheme. It also provided a cache hit ratio similar to the all-compressing counterpart and reduced 7.5% of the execution time by reducing the compression overhead. In addition, it was shown that the selective compression scheme can reduce the CPU time used for compression by 28% compared to the case of the all-compressing scheme.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.3
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• pp.166-177
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• 2006

The cache size tends to grow in the embedded processor as technology scales to smaller transistors and lower supply voltages. However, larger cache size demands more energy. Accordingly, the ratio of the cache energy consumption to the total processor energy is growing. Many cache energy schemes have been proposed for reducing the cache energy consumption. However, these previous schemes are concerned with one side for reducing the cache energy consumption, dynamic cache energy only, or static cache energy only. In this paper, we propose a hybrid scheme for reducing dynamic and static cache energy, simultaneously. for this hybrid scheme, we adopt two existing techniques to reduce static cache energy consumption, drowsy cache technique, and to reduce dynamic cache energy consumption, way-prediction technique. Additionally, we propose a early wake-up technique based on program counter to reduce penalty caused by applying drowsy cache technique. We focus on level 1 data cache. The hybrid scheme can reduce static and dynamic cache energy consumption simultaneously, furthermore our early wake-up scheme can reduce extra program execution cycles caused by applying the hybrid scheme.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.5
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• pp.2398-2415
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• 2017

Content-Centric Networking (CCN) is a new Internet architecture with routing and caching centered on contents. Through its receiver-driven and connectionless communication model, CCN natively supports the seamless mobility of nodes and scalable content acquisition. In-network caching is one of the core technologies in CCN, and the research of efficient caching scheme becomes increasingly attractive. To address the problem of unbalanced cache load distribution in some existing caching strategies, this paper presents a neighbor cooperation based in-network caching scheme. In this scheme, the node with the highest betweenness centrality in the content delivery path is selected as the central caching node and the area of its ego network is selected as the caching area. When the caching node has no sufficient resource, part of its cached contents will be picked out and transferred to the appropriate neighbor by comprehensively considering the factors, such as available node cache, cache replacement rate and link stability between nodes. Simulation results show that our scheme can effectively enhance the utilization of cache resources and improve cache hit rate and average access cost.

• Journal of the Korea Society of Computer and Information
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• v.15 no.1
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• pp.1-12
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• 2010

Recently, processor performance has been improved dramatically. Unfortunately, as the process technology scales down, energy consumption in a processor increases significantly whereas the processor performance continues to improve. Moreover, peak temperature in the processor increases dramatically due to the increased power density, resulting in serious thermal problem. For this reason, performance, energy consumption and thermal problem should be considered together when designing up-to-date processors. This paper proposes three modified filter cache schemes to alleviate the thermal problem in the filter cache, which is one of the most energy-efficient design techniques in the hierarchical memory systems : Bypass Filter Cache (BFC), Duplicated Filter Cache (DFC) and Partitioned Filter Cache (PFC). BFC scheme enables the direct access to the L1 cache when the temperature on the filter cache exceeds the threshold, leading to reduced temperature on the filter cache. DFC scheme lowers temperature on the filter cache by appending an additional filter cache to the existing filter cache. The filter cache for PFC scheme is composed of two half-size filter caches to lower the temperature on the filter cache by reducing the access frequency. According to our simulations using Wattch and Hotspot, the proposed partitioned filter cache shows the lowest peak temperature on the filter cache, leading to higher reliability in the processor.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.155-158
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• 2003

This paper proposes a quality-of-service(QoS)-adaptive proxy-switching scheme for multimedia streaming over the Internet. characteristic of multimedia-object about that effect on weight and transport-time causes Streaming Application is restricted to high-quality-service. But using of Proxy or Cache can reduce restraint of media stream. However previous scheme propose only structure of proxy and skill of streaming-object. It couldn't propose proper scheme about limited cache and proxy error occasion. We propose adaptive-proxy-switching mechanism for solution about some problems that caused by single-proxy and limited cache in case of streaming service.

• Journal of KIISE:Information Networking
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• v.27 no.2
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• pp.149-159
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• 2000

In mobile computing environments, invalidation and propagation method based on broadcasting is used to transmit the information for cache maintenance of mobile hosts. Previous researches generally adopted invalidation method that easily adapts to the limited network bandwidth and the frequent disconnection. But the invalidation of frequently accessed data causes the contention on the wireless network with the increasing cache requests. Although the propagation method can reduce the cache requests, the high probability of broken message or loss of message is the main factor that degrades the system performance. To resolve these problems, we propose adaptive cache maintenance scheme that dynamically adjusts the broadcasting ratio of invalidation and propagation, according to the wireless network connection states. The proposed scheme broadcasts the propagation message in stable connection state, so it can reduce the cache requests and server response time. With the decreasing available network bandwidth by the frequent partial disconnection and disconnection, the proposed scheme dynamically increases the broadcasting ratio of the invalidation messages to minimize the broken message or the loss of message probability. Consequently, the proposed scheme resolves the problems which arise in the invalidation or propagation method in mobile computing environments.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.12
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• pp.704-715
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• 2004

Recently, a single or multi processor system uses the hierarchical memory structure to reduce the time gap between processor clock rate and memory access time. A cache memory system includes especially two or three levels of caches to reduce this time gap. Moreover, one of the most important things In the hierarchical memory system is the hit rate in level 1 cache, because level 1 cache interfaces directly with the processor. Therefore, the high hit rate in level 1 cache is critical for system performance. A victim cache, another high level cache, is also important to assist level 1 cache by reducing the conflict miss in high level cache. In this paper, we propose the advanced high level cache management scheme based on the processor reuse information. This technique is a kind of cache replacement policy which uses the frequency of processor's memory accesses and makes the higher frequency address of the cache location reside longer in cache than the lower one. With this scheme, we simulate our policy using Augmint, the event-driven simulator, and analyze the simulation results. The simulation results show that the modified processor reuse information scheme(LIVMR) outperforms the level 1 with the simple victim cache(LIV), 6.7% in maximum and 0.5% in average, and performance benefits become larger as the number of processors increases.

• Journal of KIISE:Information Networking
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• v.29 no.3
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• pp.253-264
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• 2002

Recently, hierarchical architectures of databases for location management have been proposed in order to accommodate the increase in user population in future personal communication systems. In particular, a 3-level hierarchical database architecture is compatible with current cellular mobile systems. In the architecture, a newly developed additional databases, regional location database(RLR), are positioned between HLR and VLRs. We propose an efficient cache scheme, called the Double T-thresholds Location Cache Scheme. The cache scheme extends the existing T-threshold location cache scheme which is competent only under 2-level architecture of location databases currently adopted by IS-41 and GSM. The idea behind our scheme is to use two pieces of cache information, VLR and RLR serving called portables. The two pieces are required in order to exploit root only locality of registration area(RA) but also locality of regional registration area(RRA) which is the wide area covered by RLR. We also use two threshold values in order to determine whether the two pieces are obsolete. In order to model the RRA residence time, the branching Eralng-$\infty$ distribution is introduced. Our minute cost analysis shows that the double T-threshold location cache scheme yields significant reduction of network and database costs for molt patterns of portables.