• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.799-802
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• 2003

In this paper a FPGA implementation of WEP protocol is described. IEEE 802.11 specifies a wired LAN equivalent data confidentiality algorithm. WEP(Wired Equivalent Privacy) is defined as protecting authorized users of a wireless LAN from casual eavesdropping. WEP use RC4 algorithm for data encryption and decryption, also it use CRC-32 algorithm for error detection. The WEP protocol is implemented using Xilinx VirtexE XCV1000E-6HQ240C FPGA chip with PCI bus interface.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1053-1056
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• 1999

Video On Demand servers generally require massive disk storages for storing many video data. Many researches have been done on the topics of efficient allocation of movies in disks. This paper, We describe efficient disk placement techniques and implement storage system with SCSI and PCI Bus interface for efficient data handling. This paper also proposes a logical zone reconstruction method for the SCAN data placement technique. The proposed method reconstructs physical zones into logical zones by split and merge operations.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10a
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• pp.755-760
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• 1990

In this paper, the Mini-MAP network interface units are implemented for the IBM PC, general purpose, PLC, and robot respectively. The token bus controller, MC68824 is used to realize the IEEE 802.4. A protocol for the message exchanges between some automated devices called MMS is implemented where 76 services of total 86 MMS services are included.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.715-719
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• 2001

컴퓨터의 발달로 산업현장은 많은 부분이 자동화되고 있다. 자동화를 위해서 고려되어야 할 사항 중 하나가 입출력 디바이스 제어이다. 산업현장을 자동화하기 위해서 관련 프로그램 등이 필요하지만 이들 프로그램과 입출력 디바이스는 매우 종속적이다. 이에 본 연구에서는 COM을 이용하여 입출력 디바이스를 제어하고자 한다. 입출력 작업에 사용되는 범용 디바이스와 이를 컨트롤 할 수 있는 디바이스 드라이버를 개발하고, COM을 이용한 공장 자동화 프로그램을 개발하여 일반 사용자가 쉽게 그 기능을 사용할 뿐만 아니라 이들 프로그램을 재사용 할 수 있게 하였다.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.161-164
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• 2003

This research presents the parallel control scheme of PID servo-driver for shaping of the curved glass. The designed system consists of a PC, main controller and 11 servo-drivers. Each elements are connected by using RS-232C and 8-bit bus communication. In order to guarantee the stability and the control performance, we use the LM629, a precision PID motion controller, and LMD18200, a H-bridge on the servo-drivers. PC calculates position values of 11 DC motors by using the pre-determined curvature value and offers the user interface environment operator.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.124-127
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• 1993

This paper presents the new algorithm for fault analysis and the fault analysis package for executing this algorithm. This algorithm obtains requisite term for fault analysis by the two-port network technique. Therefore, the fault calculation time is minimized because ${Y_{BUS}}^{-1}$ calculation time is removed. And, the graphic user environment for fault analysis is implemented in mouse-oriented user interface with window and pull-down menu. Therefore, this package can be a useful tool for fault analysis.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.10
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• pp.1081-1087
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• 2008

This paper describes limitations and solutions of the existing processor-monitoring concept for a military supersonics aircraft Flight Control Computer (FLCC) equipped with modern architecture processor to perform the system integration test. Safecritical FLCC integration test, which requires automatic test for thousands of test cases and real-time input/output test condition generation, depends on the processor-monitoring device called Processor Interface (PI). The PI, which relies upon on the FLCC processor's external address and data-bus data, has some limitations due to multi-fetching capability of the modern sophisticated military processors, like C6000's VLIW (Very-Long Instruction Word) architecture and PowerPC's Superscalar architecture. Several techniques for limitations were developed and proper monitoring approach was presented for modem processor-adopted FLCC system integration test.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.869-872
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• 2005

In this paper we present a switch wrapper for an AMBA AXI, which is an efficient on-chip-network interface compared to bus-based interfaces in a multiprocessor SoC. The AXI uses an idea of NoC to provide the increasing demands on communication bandwidth within a single chip. A switch wrapper for AXI is located between a interconnection network and two IPs connecting them together. It carries out a mode of routing to interconnection network and executes protocol conversions to provide compatibility in IP reuse. A switch wrapper consists of a direct router, AHB-AXI converters, interface modules and a controller modules. We propose the design of a all-in-one type switch wrapper.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.677-680
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• 2008

AiPi technology incorporates an embedded clock and control scheme with a point-to-point bus topology, achieving the smallest possible number of interface lines between a timing controller and source drivers. A 46" AiPi-based 10-bit FHD prototype requires only 20 interface lines, compared to 38 lines for mini-LVDS. The measured maximum data rate per one data pair is more than 800Mbps.

• Proceedings of the IEEK Conference
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• 2009.05a
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• pp.246-248
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• 2009

In this paper, we will describe architecture and key characteristic for the DHS which is used in COMS. DHS is implemented in the fully redundant SCU, the dual redundant MIL-STD-1553B system bus, the payload interface units(MPIU and MI2U), the redundant ADE. the SCU interface with the other main digital units of the spacecraft through the MIL-STD-1553B.