• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.5
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• pp.1087-1095
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• 2014

A recent major development in computer technology is the advent of the wearable computer system that is based on human-centric interface technology trends and ubiquitous computing environments. Wearable computer systems can use the wireless universal serial bus (WUSB) that refers to USB technology that is merged with WiMedia PHY/MAC technical specifications. In this paper, we focus on an integrated system of the wireless USB over the IEEE 802.15.6 wireless body area networks (WBAN) for wireless wearable computer systems supporting U-health services. And a communication structure that can differentiate QoS of U-health WBAN and WUSB traffic with different priorities is proposed for WUSB over IEEE 802.15.6 hierarchical protocol. In our proposal and performance evaluation, throughputs of U-health WBAN and WUSB traffic are analyzed under single and multiple QoS classes to evaluate the effectiveness of proposed QoS differentiating structure in WUSB over IEEE 802.15.6.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.4
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• pp.839-847
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• 2014

A recent major development in computer technology is the advent of the wearable computer system that is based on human-centric interface technology trends and ubiquitous computing environments. Wearable computer systems can use the wireless universal serial bus (WUSB) that refers to USB technology that is merged with WiMedia PHY/MAC technical specifications. In this paper, we focus on an integrated system of the wireless USB over the wireless body area networks (WBAN) for wireless wearable computer systems supporting U-health services. To construct the WUSB over WBAN communication systems, we propose a WBAN beaconing structure to assign WUSB communication periods. In the proposed structure, WUSB uses private periods of WBAN. In our performance evaluations, we compare theoretical results and simulation results about throughputs of WUSB under various WBAN channel occupations to evaluate the effectiveness of proposed structure in WUSB over WBAN communications.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.145-149
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• 2011

Recently, as the design of a system gets larger and more complex, functional verification method based on system-level becomes more important. The verification of a functional block mainly uses BFM(bus functional model). The larger the burden on functional verification is, the more the importance of configuring a proper verification environment increases rapidly. SystemVerilog unifies hardware design languages and verification languages in the form of extensions to the Veri log HDL. The processing of design description, function simulation and verification using same language has many advantages in system development. In this paper, we design DUT that is composed of AMBA bus and function blocks using SystemVerilog and verify the function of DUT in verification environment using layered testbench. Adaptive FIR filter and Booth's multiplier are chosen as function blocks. We confirm that verification environment can be reused through a minor adaptation of interface to verify functions of other DUT.

• Journal of Advanced Navigation Technology
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• v.18 no.5
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• pp.437-444
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• 2014

The integrated modular avionics (IMA) system has quite a number of line repalceable moduels (LRMs) in a cabinet. The LRM performs functions like line replaceable units (LRUs) in federated architecture. The video processing module (VPM) acts as a video bus bridge and gateway of ARINC 818 avionics digital video bus (ADVB). The VPM is a LRM in IMA core system. The ARINC 818 video interface and protocol standard was developed for high-bandwidth, low-latency and uncompressed digital video transmission. FPGAs of the VPM include video processing function such as ARINC 818 to DVI, DVI to ARINC 818 convertor, video decoder and overlay. In this paper we explain how to implement VPM's Hardware. Also we show the verification results about VPM functions and IP core performance.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2914-2922
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• 1997

For FA (factory automation) and ATE (automatic test equipment) in the industrial area, the standard bus needs to increase the system performance of multiprocessor environment. VME(versa module european package format) bus is appropriated to the standard bus but has features of small package and low board density. Beside, the density of board and semiconductor have grown to become significant issues that affect development time, project cost and field diagnostics. To fit this trend, in this paper, we composed Revision C.1 (IEEE std. P1014-1987) of the integrated environment for the main function such as arbitration, interrupt and interface between, VMEbus and several control modules Also the designed, VME system controller is implemented on FPGA that can be located even into slot 1. The control and function modules are coded with VHDL mid-fixed description method and then those operations are verified by simulation. As a result of experiment, we confirmed the most important that is the operation of Bus timer about Bus error signal should occur within $56{\mu}m$, and both control and function modules have the reciprocal operation correctly. Thus, the constructed VHDL library will be able to apply the system based VMEbus and ASIC design.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.369-370
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• 2008

The Payload Interface Unit (PIU) provides the interface between payload equipment (GOCI, MODCS and Ka Band P/L) and the SCU. The PIU is a MIL-STD-1553-Bus Remote Terminal (RT). The MPIU distributes commands to, acquires telemetry from and takes part in the thermal control of the payload equipment. When in ON mode, the PIU is completely observable and can be used for payload control. When in OFF mode, the PIU is non active except the thermal control electronics.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.7
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• pp.592-598
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• 2013

In this paper, a small, lightweight smartphone-controlled riding robot is developed. Also, in this study, a smartphone with a jog shuttle mode for consideration of user convenience is proposed to make a small, lightweight riding robot. As well, a compass sensor is used to compensate for the mechanical characteristics of motors mounted on the riding robot. The riding robot is controlled by the interface of a drag-based jog shuttle in the smartphone, instead of a mechanical controller. For a personal riding robot, if the smartphone is used as a controller instead of a handle or a pole, it reduces its size, weight, and cost to a great extent. Thus, the riding robot can be used in indoor spaces such as offices for moving or a train or bus station and an airport for scouting, or hospital for disabilities. Experimental results show that the riding robot is easily and conveniently controlled by the proposed smartphone interface based on Android.

• Journal of Information Display
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• v.10 no.1
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• pp.37-44
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• 2009

AiPi technology incorporates an embedded clock and control scheme with a point-to-point bus topology, thereby having the smallest possible number of interface lines between a timing controller and column drivers. A point-to-point architecture boosts the data rate and reduces the number of interface lines, because impedance matching can be easily achieved. An embedded clock and control scheme is implemented by means of multi-level signalling, which results in a simple clock/data recovery circuitry. A 46" AiPi-based 10-bit FHD prototype requires only 20 interface lines, compared to 38 lines for mini-LVDS. The measured maximum data rate per data pair is more than 800 Mbps.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1304-1307
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• 2002

In this paper, we describe the structure and the test results of a Bluetooth baseband module we have developed. The module has a distributed buffer, i.e. FIFO, for data stream. Bus interface of the module is designed on the basis of interface of microprocessor widely used and the external interface is designed to consider chips connected directly. Since the module performs as many hardware efficient tasks as possible, processing load of microprocessor is very small. It can also be controlled either by software or by hardware for flexibility. The fully synthesizable baseband module was fabricated in a $0.25\mu\textrm{m}$ CMOS technology occupying $2.79\times2.8{\textrm{mm}^2}$ area. And an FPGA implementation of this module is tested for file and bit-stream transfers between PCs.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.153-154
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• 2008

This paper presents a window-based software package for the education and training for the reduction of power system by using locational marginal price (LMP), clustering, and similarity indices of each bus. The developed package consists of three modules: 1) the LMP module, 2) the Clustering module and 3) the Reduction module. Each module has a separated and interactive interface window. First of all, LMPs are created in the LMP module, and then the Clustering module carries out clustering based on the results of the LMP module. Finally, groups created in this Clustering module are reduced by using the similarity indices of each bus. The developed package displays a variety of tables for results of the LMPs of base network, voltages, phases and power flow of reduced network so that the user can easily understand the reduction of network. To demonstrate the performance of the developed package, it is tested for the IEEE 39-bus power system.