• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.169-173
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• 2003

We demonstrated the applicability of dry film photoresist (DFR) in photolithography process for fine pitch solder bumping on the polytetrafluoroethylene (PTFE/Teflon) printed circuit board (PCB). The copper lines were formed with $100\;{\mu}m$ width and $18\;{\mu}m$ thickness on the PTFE test board, and varying the gaps between two copper lines in a range of $100-200\;{\mu}m$. The DFRs of $15\;{\mu}m$ thickness were laminated by hot roll laminator, by varying laminating temperature from $100^{\circ}C\;to\;150^{\circ}C$ and laminating speed. We found the optimum process of DFR lamination on PTFE PCB and accomplished the formation of indium solder bumps. The optimum lamination condition was temperature of $150^{\circ}C$ and speed of about 0.63 cm/s. And the smallest size of indium solder bump was diameter of $50\;{\mu}m$ with pitch of $100\;{\mu}m$.

• ETRI Journal
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• v.36 no.4
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• pp.643-653
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• 2014

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.

• Progress in Superconductivity
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• v.3 no.1
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• pp.17-22
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• 2001

Practical implementation of the SFQ technology in most application requires more than single-chip-level circuit complexity. Multiple chips have to be integrated with a technology that is reliable at cryogenic temperatures and supports an inter-chip data transmission speed of tens of GHz. In this work, we have studied two basic issues in building large RSFQ circuits. The first is the reliable inter-chip SFQ pulse transfer technique using Multi-Chip-Module (MCM) technology. By noting that the energy contained in an SFQ pulse is less than an attojoule, it is not very surprising that the direct transmission of a single SFQ pulse through MCM solder bump connectors can be difficult and an innovative technique is needed. The second is the recycling of the bias currents. Since RSFQ circuits are dc current biased the large RSFQ circuits need serial biasing to reduce the total amount of current input to the circuit.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.73-78
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• 2016

An increase in the transistor density of integrated circuit devices leads to a very high increase in heat dissipation density, which causes a long-term reliability and various thermal problems in microelectronics. In this study, liquid cooling method was investigated using straight microchannels with various metal bumps. Microchannels were fabricated on Si wafer using deep reactive ion etching (DRIE), and Ag, Cu, or Cr/Au/Cu metal bumps were placed on Si wafer by a screen printing method. The surface temperature of liquid cooling structures with various metal bumps was measured by infrared (IR) microscopy. For liquid cooling with Cr/Au/Cu bumps, the surface temperature difference before and after liquid cooling was $45.2^{\circ}C$ and the power density drop was $2.8W/cm^2$ at $200^{\circ}C$ heating temperature.

• Korean Journal of Materials Research
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• v.22 no.10
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• pp.545-551
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• 2012

In semiconductor manufacturing, the circuit integrity of packaged BGA devices is tested by measuring electrical resistance using test sockets. Test sockets have been reported to often fail earlier than the expected life-time due to high contact resistance. This has been attributed to the formation of Sn oxide films on the Au coating layer of the probe pins loaded on the socket. Similar to contact failure, and known as "fretting", this process widely occurs between two conductive surfaces due to the continual rupture and accumulation of oxide films. However, the failure mechanism at the probe pin differs from fretting. In this study, the microstructural processes and formation mechanisms of Sn oxide films developed on the probe pin surface were investigated. Failure analysis was conducted mainly by FIB-FESEM observations, along with EDX, AES, and XRD analyses. Soft and fresh Sn was found to be transferred repeatedly from the solder bump to the Au surface of the probe pins; it was then instantly oxidized to SnO. The $SnO_2$ phase is a more stable natural oxide, but SnO has been proved to grow on Sn thin film at low temperature (< $150^{\circ}C$). Further oxidation to $SnO_2$ is thought to be limited to 30%. The SnO film grew layer by layer up to 571 nm after testing of 50,500 cycles (1 nm/100 cycle). This resulted in the increase of contact resistance and thus of signal delay between the probe pin and the solder bump.

• Korean Journal of Metals and Materials
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• v.49 no.3
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• pp.237-242
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• 2011

The effect of shearing speed on the shear force and energy of Sn-0Ag-0.5Cu solder ball was investigated. Various UBM (under bump metallurgy)'s on Cu pads were used such as ENEPIG (Electroless Nickel, Electroless Palladium, Immersion Gold; Ni/Pd/Au), ENIG (Electroless Nickel, Immersion Gold; Ni/Au), OSP (Organic Solderability Preservative). To fabricate a shear test specimen, a solder ball, $300{\mu}m$ in diameter, was soldered on a pad of FR4 PCB (printed circuit board) by a reflow soldering machine at $245^{\circ}C$. The solder bump on the PCB was shear tested by changing the shearing speed from 0.01 m/s to 3.0 m/s. As experimental results, the shear force increased with a shearing speed of up to 0.6 m/s for the ENIG and the OSP pads, and up to 0 m/s for the ENEPIG pad. The shear energy increased with a shearing speed up to 0.3 m/s for the ENIG and the OSP pads, and up to 0.6 m/s for the ENEPIG pad. With a high shear speed of over 0 m/s, the ENEPIG showed a higher shear force and energy than those of the ENIG and OSP. The fracture surfaces of the shear tested specimens were analyzed, and the fracture modes were found to have closer relationship with the shear energy than the shear force.

• ETRI Journal
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• v.34 no.5
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• pp.706-712
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• 2012

In previous work, novel maskless bumping and no-flow underfill technologies for three-dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low-volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no-flow underfill material named "fluxing underfill" is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two-tier stacked TSV chips are sucessfully stacked.

• ETRI Journal
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• v.35 no.4
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• pp.625-631
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• 2013

For the formation of solder bumps with a fine pitch of 130 ${\mu}m$ on a printed circuit board substrate, low-volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of $220^{\circ}C$. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 ${\mu}m$, 18.3 ${\mu}m$, and 12.0 ${\mu}m$, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field.

• Journal of the Korean Institute of Intelligent Systems
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• v.24 no.5
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• pp.457-461
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• 2014

Using $0.18{\mu}m$ CMOS process silicon neuron circuit of the pulse type for modeling biological neurons, were designed in the semiconductor integrated circuit. Neuron circuiSt providing is formed by MOS switch for initializing the input terminal of the capacitor to the input current signal, a pulse signal and an amplifier stage for generating an output voltage signal. Synapse circuit that can convert the current signal output of the input voltage signal, using a bump circuit consisting of NMOS transistors and PMOS few. Configure a chain of neurons for verification of the neuron model that provides synaptic neurons and two are connected in series, were performed SPICE simulation. Result of simulation, it was confirmed the normal operation of the synaptic transmission characteristics of the signal generation of nerve cells.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.4
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• pp.79-85
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• 2007

This study was focused on the feasibility of ultrasonic bonding of Au stud flip chip bumps on the flexible printed circuit board (FPCB) with three different surface finishes: organic solderability preservative (OSP), electroplated Au and electroless Ni/immersion Au (ENIG). The Au stud flip chip bumps were successfully bonded to the bonding pads of the FPCBs, irrespective of surface finish. The bonding time strongly affected the joint integrity. The shear force increased with increasing bonding time, but the 'bridge' problem between bumps occurred at a bonding time over 2 s. The optimum condition was the ultrasonic bonding on the OSP-finished FPCB for 0.5 s.