• 방사성폐기물학회지
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• 제20권4호
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• pp.541-550
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• 2022

When decommissioning nuclear power plant (NPP), the first task performed is cost estimation. This is an important task in terms of securing adequate decommissioning funds and managing the schedule. Therefore, many countries and institutions are conducting continuous research and also developing and using many programs for cost estimation. However, the cost estimated for decommissioning an NPP typically differs from the actual cost incurred in its decommissioning. This is caused by insufficient experience in decommissioning NPPs or lack of decommissioning cost data. This uncertainty in cost estimation can be in general compensated for by applying a contingency. However, reflecting an appropriate standard for the contingency is also difficult. Therefore, in this study, data analysis was conducted based on the contingency guideline suggested by each institution and the actual cost of decommissioning the NPP. Subsequently, TLG Service, Inc.'s process, which recently suggested specific decommissioning costs, was matched with ISDC (International Structure for Decommissioning Costing)'s work breakdown structure (WBS). Based on the matching result, the guideline for applying the contingency for ISDC's WBS Level 1 were presented. This study will be helpful in cost estimation by applying appropriate contingency guidelines in countries or institutions that have no experience in decommissioning NPPs.

• 기술혁신연구
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• 제16권1호
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• pp.107-139
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• 2008

We studied how to achieve successful implementation of massive research and development projects requiring collaboration among industries, universities and government-supported research institute. We have set up an engineering process innovation model to be deemed most adequately for all practical purposes, relying on the theoretical studies on the merits and analysis of the effect of the information system based on Milestone Management, Work Breakdown Structures and Web, which is known to be effective for research project (schedule) management and the objective management, and implemented a real-world web-based project objective management system. After a review of various R & D Project Schedule Management methods, we found that this information system was very compatible with project objective management. This project objective management information system carries out research and development projects effectively and efficiently, getting together in cyber-space and sharing information, and has been equipped with an Early Warning Subsystem to allow for pre-analysis and timely response to potential problems arising from the course of the project. The system also contains an Executive Information System that in real time, automatically provides the management information required by managers with the rate of project progress (achievement, fulfillment and delay). Lastly, actual progress can be cross-checked through both on-line objective management on the web-based information system and design review meeting held on site, to improve the efficiency and validity of the information system. Moreover, overall effect was analyzed through questionnaires on how well the system and generated information meet requirements and on the ultimate impact of the system upon objective management and communication. The questionnaire on the system effect revealed that the information system was useful to objective management and communication, and that the quality of the system was more than acceptable as well.

• 한국전자통신학회논문지
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• 제8권8호
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• pp.1227-1234
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• 2013

1.2 더블 폴리 부유게이트 트랜지스터로 구성된 아날로그 메모리가 CMOS 표준공정에서 제작되었다. 효율적인 프로그래밍을 위해 일반적인 아날로그 메모리에서 사용되었던 불필요한 초기 소거 동작을 제거하였으며 프로그래밍과 읽기의 경로를 동일하게 가져감으로서 읽기 동작 시에 발생하는 증폭기의 DC 오프셋 문제를 근본적으로 제거하였다. 어레이의 구성에서 특정 셀을 주변의 다른 셀들로부터 격리시키는 패스 트랜지스터 대신에 Vmid라는 별도의 전압을 사용하였다. 실험 결과 아날로그 메모리가 디지털 메모리의 6비트에 해당하는 정밀도를 보였으며 프로그래밍 시에 선택되지 않은 주변의 셀들에 간섭 효과가 없는 것으로 확인되었다. 마지막으로, 아날로그 어레이를 구성하는 셀은 특이한 모양의 인젝터 구조를 가지고 있으며, 이것은 아날로그 메모리가 특별한 공정 없이도 트랜지스터의 breakdown 전압 아래에서 프로그래밍 되도록 하였다.

• Transactions on Electrical and Electronic Materials
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• 제14권3호
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• pp.121-124
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• 2013

The incorporation of 90 nm alumina particles into an epoxy matrix to form a composite microstructure is described in present study. It is shown that the use of ultrafine particles results in a substantial change in the behavior of the composite, which can be traced to the mitigation of internal charges when a comparison is made with conventional $Al_2O_3$ fillers. A variety of diagnostic techniques have been used to augment pulsed electro-acoustic space charge measurement to provide a basis for understanding the underlying physics of the phenomenon. It would appear that, when the size of the inclusions becomes small enough, they act cooperatively with the host structure and cease to exhibit interfacial properties. It is postulated that the $Al_2O_3$ particles are surrounded by high charge concentrations. Since $Al_2O_3$ particles have very high specific areas, these regions allow limited charge percolation through $Al_2O_3$ filled dielectrics. The practical consequences of this have also been explored in terms of the electric strength exhibited. It would appear that there was a window in which real advantages accumulated from the nano-formulated material. An optimum filler loading of about 0.5 wt.% was indicated.

• 대한전자공학회논문지SD
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• 제44권8호
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• pp.45-51
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• 2007

[ $1.6{\mu}m$ ]의 활성층을 가지는 planar형태의 94 GHz graded-gap injector GaAs 건 다이오드를 설계, 제작하였다. 이 다이오드는 반 절연 기판에 성장된 에피 구조를 바탕으로 메사 식각, 오믹 금속 접촉형성 및 overlay metalization의 주요 공정을 통하여 두가지 형태의 planar 구조로 제작되었다. 제작된 건 다이오드의 부성저항 특성을 anode와 cathode 금속전극들의 배치를 달리 한 두 소자 구조에서 고찰하였고 graded-gap injector의 역할을 순방향과 역방향에서의 직류거동으로부터 살펴보았다. 결과적으로, 금속전극의 배치에 있어서, cathode와 anode 전극사이의 거리가 감소된 소자 구조에서 증가된 peak 전류와 breakdown 전압, 그리고 감소된 문턱전압을 얻었다.

• 전기학회논문지
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• 제61권11호
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• pp.1646-1649
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• 2012

The $O_2$ annealing technique has considerably suppressed the leakage current of GaN power devices, but this forms NiO at Ni-based Schottky contact with increasing on-resistance. The purpose of the present study was to fabricate 1.5 kV GaN Schottky barrier diodes by improving $O_2$-annealing process and GaN buffer. The proposed $O_2$ annealing performed after alloying ohmic contacts in order to avoid NiO construction. The ohmic contact resistance ($R_C$) was degraded from 0.43 to $3.42{\Omega}-mm$ after $O_2$ annealing at $800^{\circ}C$. We can decrease RC by lowering temperature of $O_2$ annealing. The isolation resistance of test structure which indicated the surface and buffer leakage current was significantly increased from $2.43{\times}10^7$ to $1.32{\times}10^{13}{\Omega}$ due to $O_2$ annealing. The improvement of isolation resistance can be caused by formation of group-III oxides on the surface. The leakage current of GaN Schottky barrier diode was also suppressed from $2.38{\times}10^{-5}$ to $1.68{\times}10^{-7}$ A/mm at -100 V by $O_2$ annealing. The GaN Schottky barrier diodes achieved the high breakdown voltage of 700, 1400, and 1530 V at the anode-cathode distance of 5, 10, and $20{\mu}m$, respectively. The optimized $O_2$ annealing and $4{\mu}m$-thick C-doped GaN buffer obtained the high breakdown voltage at short drift length. The proposed $O_2$ annealing is suitable for next-generation GaN power switches due to the simple process and the low the leakage current.

• 한국주조공학회지
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• 제21권4호
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• pp.253-259
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• 2001

There are many methods to produce metal foams, which can be classified into three groups according to the state of the starting metal i.e. liquid or powder or solid. Three types of defects such as cell closing, cell deformation or breakdown and cell misrun are thought to be occurred when we make the open cell aluminum foams by precision casting. Filling ability of the mold slurry between preform is related with cell closing, mold collapsibility is related with cell deformation or breakdown, mold temperature and pouring pressure are related with cell misrun. These factors can be evaluated by measuring slurry fluidity, burnout strength and permeability of the mold. Properties of the plaster mold were evaluated to find optimum mold conditions for high quality open cell aluminum foam in this study. Permeability was almost zero independent of burnout conditions, however, crack initiation was found on the surface of all specimens one or two minutes after taking out from the furnace. Crack has grown and disappeared with time. This crack may facilitate the mold filling when molten metal is poured, because of the improved mold permeability. It was considered that crack initiation and disappearance was closely related with temperature difference between the surface and inner part. Knocking-out the mold is a difficult problem due to the small cell size, because continuous mesh structure of the metal foam is not strong. It is not easy to remove molding material after pouring. We can expect that water quenching can facilitate the knocking-out the mold after solidification without damaging cell structures. Collapsed particles after water quenching became bigger with the increase in time.

• 반도체디스플레이기술학회지
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• 제13권3호
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• pp.45-50
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• 2014

In this paper, we propose a super-junction MOSFET (SJ MOSFET) fabricated through a simple pillar forming process by varying the Si epilayer thickness and doping concentration of pillars using SILVACO TCAD simulation. The design of the SJ MOSFET structure is presented, and the doping concentration of pillar, breakdown voltage ($V_{BR}$) and drain current are analyzed. The device performance of conventional Si planar metal-oxide semiconductor field-effect transistor(MOSFET), Si SJ MOSFET, and SiGe SJ MOSFET was investigated. The p- and n-pillars in Si SJ MOSFET suppressed the punch-through effect caused by drain bias. This lead to the higher $V_{BR}$ and reduced on resistance of Si SJ MOSFET. An increase in the thickness of Si epilayer and decrease in the former is most effective than the latter. The implementation of SiGe epilayer to SJ MOSFET resulted in the improvement of $V_{BR}$ as well as drain current in saturation region, when compared to Si SJ MOSFET. Such a superior device performance of SiGe SJ MOSFET could be associated with smaller bandgap of SiGe which facilitated the drift of carriers through lower built-in potential barrier.

• 전자공학회논문지C
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• 제35C권10호
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• pp.30-37
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• 1998

1.2㎛ 더블 폴리 부유게이트 트랜지스터로 구성된 아날로그 메모리가 CMOS 표준공정에서 제작되었다. 효율적인 프로그래밍을 위해 일반적인 아날로그 메모리에서 사용되었던 불필요한 초기 소거 동작을 제거하였으며 프로그래밍과 읽기의 경로를 동일하게 가져감으로서 읽기 동작 시에 발생하는 증폭기의 DC offset 문제를 근본적으로 제거하였다. 어레이의 구성에서 특정 셀을 주변의 다른 셀들로부터 격리시키는 패스 트랜지스터 대신에 Vmid라는 별도의 전압을 사용하였다. 실험 결과 아날로그 메모리가 디지털 메모리의 6비트에 해당하는 정밀도를 보였으며 프로그래밍 시에 선택되지 않은 주변의 셀들에 간섭 효과가 없는 것으로 확인되었다. 마지막으로, 아날로그 어레이를 구성하는 셀은 특이한 모양의 인젝터 구조를 가지고 있으며, 이것은 아날로그 메모리가 특별한 공정 없이도 트랜지스터의 breakdown 전압 아래에서 프로그래밍 되도록 하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권1호
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• pp.66-77
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• 2010

Improvement in breakdown voltage ($BV_{ds}$) and speed of the device are the key issues among the researchers for enhancing the performance of HEMT. Increased speed of the device aspires for shortened gate length ($L_g$), but due to lithographic limitation, shortening $L_g$ below sub-micrometer requires the inclusion of various metal-insulator geometries like T-gate onto the conventional architecture. It has been observed that the speed of the device can be enhanced by minimizing the effect of upper gate electrode on device characteristics, whereas increase in the $BV_{ds}$ of the device can be achieved by considering the finite effect of the upper gate electrode. Further, improvement in $BV_{ds}$ can be obtained by applying field plates, especially at the drain side. The important parameters affecting $BV_{ds}$ and cut-off frequency ($f_T$) of the device are the length, thickness, position and shape of metal-insulator geometry. In this context, intensive simulation work with analytical analysis has been carried out to study the effect of variation in length, thickness and position of the insulator under the gate for various metal-insulator gate geometries like T-gate, $\Gamma$-gate, Step-gate etc., to anticipate superior device performance in conventional HEMT structure.