• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.79-88
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• 2009

In boundary scan architecture, test stimuli are shifted in one at a time and applied to the on-chip system logic. The test results are captured into the BSR and are examined by subsequent shifting. In this paper, we developed a continuous capture test architecture and test procedure using TPG based on boundary scan is used to performance test. In this architecture, test patterns of TPG are applied to CUT with system clock rate, and response of CUT is continuously captured by CBSR(Continuous Capture Boundary Scan Register) at the same rate and the captured results is shifted to TDO at the same rate. The suggested a continuous capture test architecture and test procedure is simulated by Altera Max+Plus 10.0. The simulation results shows the accurate operation and effectiveness of the proposed test architecture and procedure.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.12
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• pp.675-682
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• 2000

When a system is composed of multi-boards, an efficient bus arbitration method for the data transfer bus must be provided for guaranteeing proper operations. In this paper, a new test methodology is developed which is used for testing on-line bus arbitration. In the new test methodology, events that are occurred during bus arbitration are defined, and expected signals during fault-free bus arbitration are compared with the signals captured during on-line bus arbitration using boundary-scan cells. For this, a new test architecture is proposed which is efficient for the maintenance and the repair of multi-board systems. In addition, the new methodology can be used with off-line interconnect test using boundary-scan.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.2
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• pp.151-157
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• 1990

This paper presents a method for rapid wire frame drawing of the 3D objects represented by the CSG scheme. When the two CSG trees are combined into one, the intersection parts of the polygons constituting the object corresponds to each subtree are computed, and the boundary representation of the combined object is obtained according to the given combinational operator and stored in the root node. The boundary representation in the root node is used in the wireframe drawing of the object and later computation of boundary representation. Bezier surface is taken as one of the primitive object the scan-line algorithm is used, which subdivides each scan-line into the spans where no polygon is intersected, and renders each span with the CSG representation of the object.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1A
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• pp.66-72
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• 2002

In this paper, we implemented the GenJTAG, a CAD tool, which generates a code of boundary scan circuit supporing a board level testing and d BIST(Built-In Self Test) written in verilog-HDL. A boundary scan circuit code that supports user's own BIST instructions is generated based on the informations from the users. Most CAD tools hardly allow users to add their own BIST instructions because the generated code described in gate-level. But the GenJTAG generates a behavioral boundary scan circuit code so users can easily make a change on the generated code.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.197-200
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• 2002

We newly developed the procedures of X-ray Cargo inspection system with acquisition of multi-channel data, analog to digital converter and post logic circuit which is controlled by the FPGA. The IEEE1149.1 standard defines a four-wire serial interface(a fifth wire is optional)to access complex integrated circuits(ICs) such as PLD. This paper describes that Boundary_Scan test method applied to our home made cargo inspection system.

• Journal of the Korean Society for Nondestructive Testing
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• v.15 no.1
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• pp.299-309
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• 1995

A geometrical inverse heat conduction problem is solved for the development of Infrared Computerized-Axial-Tomography (IR CAT) Scan by using a boundary element method in conjunction with regularization procedure. In this problem, an overspecified temperature condition by infrared scanning is provided on the surface, and is used together with other conditions to solve the position of an unknown boundary (cavity). An auxiliary problem is introduced in the solution of this problem. By defining a hypothetical inner boundary for the auxiliary problem domain, the cavity is located interior to the domain and its position is determined by solving a potential problem. Boundary element method with regularization procedure is used to solve this problem, and the effects of regularization on the inverse solution method are investigated by means of numerical analysis.

• Proceedings of KOSOMES biannual meeting
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• 2005.11a
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• pp.197-202
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• 2005

Generally, a semiconductor chip measured with a few micro units is captured by line scan camera for higher inspection accuracy. However, the faulty inspection requires an exact boundary detection algorithm because it is very sensitive to scan speed and lighting conditions. In this paper we propose boundary detection using subpixel edge detection method in order to increase the accuracy of bump faulty detection on chips. The bump edge is detected by first derivative to four directions from bump center point and the exact edge positions are searched by the subpixel method. Also, the exact bump boundary to calculate the actual bump size is computed by LSM(Least Squares Method) to minimize errors since the bump size is varied such as bump protrusion, bump bridge, and bump discoloration. Experimental results exhibit that the proposed algorithm shows large improvement comparable to the other conventional boundary detection algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.793-799
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• 2007

Generally, a semiconductor chip measured with a few micro units is captured by line scan camera for higher inspection accuracy. However, the faulty inspection requires an exact boundary detection algorithm, because it is very sensitive to scan speed and lighting conditions. In this paper we propose boundary detection with subpixel edge detection in order to increase the accuracy of bump faulty detection on chips. The bump edge is detected by first derivative to four directions from bump center point and the exact edge positions are searched by the subpixel method. Also, the exact bump boundary to calculate the actual bump size is computed by LSM(Least Squares Method) to minimize errors since the bump size is varied such as bump protrusion, bump bridge, and bump discoloration. Experimental results exhibit that the proposed algorithm shows large improvement comparable to the other conventional boundary detection algorithms.

• Journal of the Korea Society of Computer and Information
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• v.13 no.4
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• pp.87-95
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• 2008

In this paper, we developed a selectable observation Point test architecture and test procedure for clocked 4-bit synchronous counter circuit based on boundary scan architecture. To develope, we analyze the operation of Sample/Preload instruction on boundary scan architecture. The Sample/Preload instruction make Possible to snapshot of outputs of CUT(circuit under test) at the specific time. But the changes of output of CUT during normal operation are not possible to observe using Sample/Preload in typical scan architecture. We suggested a selectable observation point test architecture that allows to select output of CUT and to observe of the changes of selected output of CUT during normal operation. The suggested a selectable observation point test architecture and test procedure is simulated by Altera Max 10.0. The simulation results of 4-bit counter shows the accurate operation and effectiveness of the proposed test architecture and procedure.

• Proceedings of the KIEE Conference
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• 2003.10a
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• pp.258-260
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• 2003

In this paper, we study the reduction of the Dynamic False Contour in a new driving method. This method divides scan lines into Multi Blocks, and drives both selective write and selective erase address. Because of the characteristic of proposed waveform, each scan line has a different sustain pulse weight. Therefore, the Dynamic False Contour occurs seriously in the boundary of each Block. Finally, if scan-lines tie several lines, the Dynamic False Contour can reduce in the boundary of each Block.