• 한국정보통신학회논문지
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• 제21권8호
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• pp.1465-1470
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• 2017

기존의 MOSFET에서는 반전층보다 항상 실리콘 두께가 크기 때문에 드레인유도 장벽감소가 실리콘 두께에 관계없이 산화막 두께 및 채널길이의 함수로 표현되었다. 그러나 10 nm 이하 저도핑 이중게이트 구조에서는 실리콘 두께 전체가 공핍층이 형성되기 때문에 기존의 SPICE 모델을 사용할 수 없게 되었다. 그러므로 이중게이트 MOSFET에 대한 새로운 SPICE 용 드레인유도 장벽감소 모델을 제시하고자 한다. 이를 분석하기 위하여 전위분포와 WKB 근사를 이용하여 열방사 및 터널링 전류를 구하였다. 결과적으로 드레인유도 장벽감소는 상하단 산화막 두께의 합 그리고 실리콘 두께의 2승에 비례하며 채널길이의 3승에 반비례한다는 것을 알 수 있었다. 특히 SPICE 파라미터인 정적 궤환계수가 1과 2사이에서 사용할 수 있어 합당한 파라미터로써 사용할 수 있었다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.107-108
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• 2008

The spectacular development of AMLCDs, been made possible by a-Si:H technology, still faces two major drawbacks due to the intrinsic structure of a-Si:H, namely a low mobility and most important a shift of the transfer characteristics of the TFTs when submitted to bias stress. This has lead to strong research in the crystallization of a-Si:H films by laser and furnace annealing to produce polycrystalline silicon TFTs. While these devices show improved mobility and stability, they suffer from uniformity over large areas and increased cost. In the last decade we have focused on microcrystalline silicon (${\mu}c$-Si:H) for bottom gate TFTs, which can hopefully meet all the requirements for mass production of large area AMOLED displays [1,2]. In this presentation we will focus on the transfer of a deposition process based on the use of $SiF_4$-Ar-$H_2$ mixtures from a small area research laboratory reactor into an industrial gen 1 AKT reactor. We will first discuss on the optimization of the process conditions leading to fully crystallized films without any amorphous incubation layer, suitable for bottom gate TFTS, as well as on the use of plasma diagnostics to increase the deposition rate up to 0.5 nm/s [3]. The use of silicon nanocrystals appears as an elegant way to circumvent the opposite requirements of a high deposition rate and a fully crystallized interface [4]. The optimized process conditions are transferred to large area substrates in an industrial environment, on which some process adjustment was required to reproduce the material properties achieved in the laboratory scale reactor. For optimized process conditions, the homogeneity of the optical and electronic properties of the ${\mu}c$-Si:H films deposited on $300{\times}400\;mm$ substrates was checked by a set of complementary techniques. Spectroscopic ellipsometry, Raman spectroscopy, dark conductivity, time resolved microwave conductivity and hydrogen evolution measurements allowed demonstrating an excellent homogeneity in the structure and transport properties of the films. On the basis of these results, optimized process conditions were applied to TFTs, for which both bottom gate and top gate structures were studied aiming to achieve characteristics suitable for driving AMOLED displays. Results on the homogeneity of the TFT characteristics over the large area substrates and stability will be presented, as well as their application as a backplane for an AMOLED display.

• 건축역사연구
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• 제25권4호
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• pp.57-64
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• 2016

It was believed that Jeongnimsa temple was built after the capital was moved from Gongju to Buyeo. It was confirmed that it was built A.D. $625{\pm}20$ by conducting a paleomagnetic analysis on the fireplace, which was recently found at the bottom of Jungmunji(middle gate). Consequently, it is assumed that the temple was built in the early 7th century unlike the previous point of view. Therefore, this study evaluated if the fireplace at the bottom of Jungmunji was found at the geological stratum representing the Jeongnimsa temple. Moreover, the study examined when the fireplace at the bottom of Jungmunji was constructed on the soil stratum. It is possible that the fireplace was built in the early 7th century as shown in the paleomagnetic analysis. However, when we compared the soil strata of the Jungmunji and the existing five-story stone pagoda, it showed that the ground was prepared differently and they were built over a fairly long period of time. Furthermore, I discovered that there was a wooden pagoda under the five-story stone pagoda by examining the soil strata map. Therefore, previous studies evaluated the arrangement of auxiliary buildings of Jeongnimsa temple and concluded that it was built in the early 7th century. It is hard to determine when the temple was built based on the arrangement of auxiliary buildings, because it takes a long time to build a temple and auxiliary buildings can be relocated during this long construction period. Rather, we have to admit that there are various arrangement patterns through minor changes in buildings from the one pagoda and one main building(Geumdang) arrangement.

• 한국해안해양공학회지
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• 제10권1호
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• pp.18-26
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• 1998

금강하구에서 대규모 공사의 영향으로 인한 수동역학적 변화를 해석하기 위하여, 2차원 유한요소 수동역학모형을 적용하었다. 수치모형을 조석과 조류번화 해석에 적용한 결과 금강하구둑의 수문이 열렸을 때와 eke혔을 때는 조석체계가 급격히 변화되어 M$_2$, 분조가 각각 군산내항에서 17 cm 및 6 cm 확폭되고, 군산외항에서는 5 cm 및 3 cm 확폭되는 것을 알 수 있었다. 연차별 단계별로 진척되는 공사로 인한 조류와 해저 퇴적성향의 변화결과는 도류제 축조로 조류속이 증가되는 것이 뚜렷하게 나타났으며, 금강하구역의 동적평형을 이루는 해저마찰응력은 0.4N/$m^2$로 분석되었다. 일대해역의 퇴적율 R은 최대마찰응력(equation omitted)와 상관이 있으며 R=-0.37-0.40 ln $\tau$의 관계로 설명된다.

• 한국환경과학회지
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• 제18권9호
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• pp.971-981
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• 2009

An objective of this study is as follows: 1) performing sensitivity analysis and parameter estimation of RMA2 and RMA4 models for the West-Nakdong River, 2) drawing up alternatives of gates-operation for water-quality enhancement, and 3) quantitative evaluation of methodology of 'flow-restoration by gates-operation' among 'Comprehensive Plan Improving Water-Quality in the West-Nakdong River(WNR)' with the target water-quality(BOD at Nakbon-N point: below 4.3 mg/L). The parameters for the RMA2 (depth-averaged two-dimensional flow model) and RMA4 (depth-averaged two-dimensional water-quality model) were determined by sensitivity analysis. Result of parameter estimation for RMA2 and RMA4 models is $1,000\;Pa{\cdot}s$ of the eddy viscosity, 20 of the Peclet number, 0.025 of the Manning coefficient, and $1.0\;m^2/s$ of the diffusion coefficient. We have evaluated the effects of water-quality enhancement of the selected alternatives by numerical simulation technique with the models under the steady-state flow condition and the time-variant transport condition. Because of no-resuspension from river bottom and considering BOD as conservative matter, these simulation results slightly differ from real phenomena. In the case of $50\;m^3/s$ of Daejeo-gate inflow, two-dimensional flow pn results result represents that small velocity occurs in the Pyungkang Stream and no flow in the Maekdo River. In the WNR, there occurs the most rapid flow near timhae-bridge. In the WNR, changes of water-quality for the four selected simulation cases(6, 10, 30, $50\;m^3/s$ of the Daejeo-gate inflow) were predicted. Since the Daejeo-Gate and the Noksan-Gate can be opened up to 7 days, it would be found that sustainable inflow of $30\;m^3/s$ at the Daejeo-gate makes BOD in the WNR to be under the target of water-quality.

• Transactions on Electrical and Electronic Materials
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• 제16권2호
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• pp.62-64
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• 2015

We have investigated zinc tin oxide (ZTO) thin films under various silicon ratios. ZTO TFTs were fabricated by solution processing with the bottom gate structure. Furthermore, annealing process was performed at different temperatures in various annealing conditions, such as air, vacuum and wet ambient. Completed fabrication of ZTO TFT, and the performance of TFT has been compared depending on the annealing conditions by measuring the transfer curve. In addition, structure in ZTO thin films has been investigated by X-ray diffraction spectroscopy (XRD) and Scanning electron microscope (SEM). It is confirmed that the electrical performance of ZTO TFTs are improved by adopting optimized annealing conditions. Optimized annealing condition has been found for obtaining high mobility.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1342_1342
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• 2009

Zinc tin oxide (ZTO) based thin-film transistors (TFTs) were fabricated on glass substrate by using sol-gel method. The fabricated ZTO TFT had bottom gate and top contact structure with ZTO layer formed by spin coating from ZTO solution. The fabricated TFT showed field-effect mobility of about 2 - $4\;cm^2/V{\cdot}s$ with on/off current ratios >$10^7$, and threshold voltage of 2 V.

• 한국농공학회지
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• 제36권4호
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• pp.33-38
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• 1994

Floating-type automatic turnout was developed for the purpose of reducing labor cost and labor-working hours related to turnout management. The point of automation is to use a flexible-float within the turnout. The weight of float is changed by emptying and filling with water at the beginning and ending of irrigation. The turnout is controlled to open and close small bole on the float bottom using electromagnets. With the weight control of float. the gate of turnout is opened by the empty float to begin irrigatiom and is closed by the filled float to stop irrigation. The turnout was designed to be operated by the main computer and to minimize electric power consumption by sending an electric current at the beginning and ending of irrigation. The functional experiment was succesfully carried out and the rating curves for both free overflow condition and submerged flow condition were derived.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.132-135
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• 2000

We have been aware fer some time. that it is becoming harder to develop ASIC only, using the vendor wire model for the current top-down/bottom-up process. Because VDSM has a much bigger wired delay than cell delay, it is also difficult to reduce development time, as well as time-to-market, while developing several million gate ASIC's. The same is true for high frequency ASIC's with VDSM (which have larger wire delay versus cell delay). Therefore, a solution called “RTS-GDS”, using physical constraints fur SOC with timing met, is being actively discussed. This paper suggests a methodology for SOC development by utilizing a top down flow via CWLM along with discussing potential problems. This paper also provides a design flow, including physical synthesis, DFT, floor plan and CWLM, all of which are relevant to proper SOC development.

• 한국결정성장학회지
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• 제12권3호
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• pp.161-164
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• 2002

Polycrystalline and epitaxial heterostructure films of $La_{0.5}Sr_{0.5}CoO_{3}/Pb(Nb_{0.04}Zr_{0.28}Ti_{0.68})O_{3}/La_{0.5}Sr_{0.5}CoO_{3}$ (LSCO/PNZT/LSCO) capacitors were evaluated in terms of low voltage and high speed operation in high density memory, using TiN/Pt conducting barrier combination. Structural studies for a high density ferroelectric memory process flow, which requires the integration of conducting barrier layers to connect the drain of the pass-gate transistor to the bottom electrode of the ferroelectric stack, indicate complete phase purity (i.e. fully perovskite) in both epitaxial and polycrystalline materials. The polycrystalline capacitors show lower remnant polarization and coercive voltages. However, the retention, and high-speed characteristics are similar, indicating minimal influence of crystalline quality on the ferroelectric properties.