• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.183-184
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• 2007

A 40 Gb/s transimpedance amplifier IC was designed and fabricated with a InP/InGaAs HBTs technology. In this study, we interconnect 40Gbps trans impedance amplifier IC to a duroid substrate by a flip chip bonding instead of conventional wire bonding for interconnection. For flip chip bonding, we developed fine pitch bump with the $70{\mu}m$ diameter and $150{\mu}m$ pitch using WLP process. To study the effect of WLP, electrical performance was measured and analyzed in wafer and package module using WLP. The Small signal gains in wafer and package module were 7.24 dB and 6.93dB respectively. The difference of small signal gain in wafer and package module was 0.3dB. This small difference of gain is due to the short interconnection length by bump. The characteristics of return loss was under -10dB in both wafer and module. So, WLP process can be used for millimeter wave GaAs MMIC with the fine pitch pad and duroid substrate can be used in flip chip bonding process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.390-391
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• 2006

This paper describes the design, fabrication and characteristics of a micromachined piezoelectric valve utilizing a multilayer ceramic actuator (MCA). The micromachined MCA valve, which uses a buckling effect, consists of three separate structures: the MCA, the valve actuator die and the seat die. The valve seat die with 6 trenches was made, and the actuator die, which is driven by the MCA under optimized conditions, was also fabricated. After Si wafer direct bonding between the seat die and the actuator die, the MCA was also anodically bonded to the seat/actuator die structure. A polydimethylsiloxane (PDMS) sealing pad was fabricated to minimize the leak rate. Finally, the PDMS sealing pad was also bonded to the seat die and the stainless steel package. The MCA valve shows a flow rate of 9.13 sccm at an applied DC voltage of 100 V with a 50% duty cycle and a maximum non-linearity of 2.24% FS. Therefore, the fabricated MCA valve is suitable for a variety of flow control equipment, as a medical bio-system and in the automobile industry.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.69-73
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• 2008

This article shows that the susceptibility of the device pattern to thermal stress-induced damage has a strong dependence on its proximity to the device comer in semiconductor devices utilizing lead-on-chip (LOC) die attach technique. The result, as explained based on numerical calculation and experiment, indicateds that the stress-driven damage potential of the passivation layer is the highest at the device comer. Thus, the bonding pads, which are very susceptible to passivation damage, should be designed to be located along the central region rather than the peripheral region of the device.

• Journal of Welding and Joining
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• v.19 no.3
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• pp.311-316
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• 2001

This paper presents that the affecting factors to the solderability and initial reliability. It is the factor that the coefficient of thermal expansion between package and PCB(Printed Circuit Board), the quantity of solder paste and reflow condition, and Au thickness of the solder ball pad on polyimide tape. As the reflow soldering condition for 48 ${\mu}BGA$ is changed, it is estimated that the quantity of Au diffusion at eutectic Sn-Pb solder surface and initial bonding strength of eutectic Sn-Pb solder and lead free solder. It is the result that quantitative measurement of Au diffusion quantity is difficult, but the shear strength of eutectic Sn-Pb solder joint is 842 mN at first reflow and increases 879 mN at third reflow. The major failure mode in solder is judged solder fracture. So, Au diffusion quantity is more affected by reflow temperature than by the reflow times.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.333-336
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• 2000

This paper describes a CMOS low noise amplifier (LNA) with bias current reusing architecture intended lot use in the front-end of IMT-2000 receiver. It has been implemented in a 0.35$\mu\textrm{m}$ CMOS process with two poly and four metal layers. In order to accuracy of simulation, we considered a bonding wire and a pad effect and used the measurements of capacitors and on-chip inductors which implemented in the same process. The LNA has a forward gain (S21) of 17 ㏈ and a noise fjgure of 1.26 ㏈. And it has a third-order intermodulation intercept point (IP3) of +3.15 ㏈m and a 1㏈ compression point (P1㏈) of -16 ㏈m, input referred, respectively. The power consumption is 19 ㎽ from a 3V supply.

• Journal of Welding and Joining
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• v.16 no.5
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• pp.100-107
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• 1998

This paper describes fluxless soldering of reflow soldering process using solder foil instead of solder pastes. There is an increasing demand for the reliable solder connection in the recent high density microelectronic components technologies. And also, it is problem fracture of an Ozone layer due to freon as which is used to removal of remained flux on the substrate. This paper discussed joining phenomena, boudability and joining processes of microelectronics devices, such as between outer lead of VLSI package and copper pad on a substrate without flux. The shear strength of joints is 8 to 13 N using Sn/Pb (63/37 wt.%) solder foil with optimum joining conditions, meanwhile, in case of using Sn/In (52/48 wt.%) solder foil, it is possible to bond with low heating temperature of 550 K, and accomplish to high bonding strength of 25N in condition heating temperature of 650K. Finally, this paper experimentally shows fluxless soldering using solder foil, and accomplishes key technology of microsoldering processes.

• Proceedings of the KWS Conference
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• 2005.11a
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• pp.231-233
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• 2005

Laser have been utilized as a heat source for the soldering of electronic components for the their capability of localized heating and faster heating rate. Laser soldering process, especially the diode laser soldering of BGA solderball was investigated. In this study, an attempt was made to investigate the possibility of laser soldering using Sn-37Pb and Sn-3Ag-0.5Cu solderball. The laser energy absorbed on the pad raised the temperature of the solderball forming a reflowed solder bump. The result were discussed based on the measurement of pull and shear strength of the bond.

• Journal of the Microelectronics and Packaging Society
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• v.2 no.1
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• pp.59-68
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• 1995

박막제조 기술 및 BGA패캐지를 이용하여 Wellcom 2000 system 소요 OCU Board 의 집적화를 구현하였다. 기존 PCB에 실장되는 소자 일부를 2 Channel BGA 패캐지로 모 듈화한 결과 약 1/6로 소형화시킬수 있었으며 8 Channel의 모율화는 현재 진행중인 다층 구조의 제조 기술 개발과 아울러 BGA 패캐지로 실현이 가능하며 1/10로집접화할수 있음을 알수 있었다. 또한 PCB위에 Bare Chip을 실장하여 Wire Bonding 한 COB를 구현하여 CBGGA의 PCB실장과 함께한 모듈을 형성해 보았다. CBGA패캐지에 Ball Shear Test, In Circuit Test 온도 환경주기시험(TCT) 진동시험을 통하여 신뢰성을 입증하였다. 이때 CBGA의 Coplanarity(3.2%) 증진을 위하여 Ceramic Pad에 선택적인 도금 방식을 개발적용 하였다.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.1
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• pp.33-38
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• 2007

We studied a bonding at low temperature using polymer bump and Non-Conductive Adhesive (NCA), and studied the reliability of the polymer bump/Al pad joints. The polymer bumps were formed on oxidized Si substrates by photolithography process, and the thin film metals were formed on the polymer bumps using DC magnetron sputtering. The substrate used was AL metallized glass. The polymer bump and Al metallized glass substrates were joined together at $80^{\circ}C$ under various pressure. Two NCAs were applied during joining. Thermal cycling test ($0^{\circ}C-55^{\circ}C$, cycle/30 min) was carried out up to 2000 cycles to evaluate the reliability of the joints. The bondability was evaluated by measuring the contact resistance of the joints through the four point probe method, and the joints were observed by Scanning Electron Microscope (SEM). The contact resistance of the joints was $70-90m{\Omega}$ before the reliability test. The joints of the polymer bump/Al pad were damaged by NCA filler particles under pressure above 200 MPa. After reliability test, some joints were electrically failed since thinner metal layers deposited at the edge of bumps were disconnected.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.40-50
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• 2023

Recently, the number of components of smartphones increases rapidly, while the PCB size continuously decreases. Therefore, 3D technology with a stacked PCB has been developed to improve component density in smartphone. For the s tacked PCB, it i s very important to obtain solder bonding quality between PCBs. We investigated the effects of the properties, thickness, and number of layers of interposer PCB and sub PCB on warpage of PCB through experimental and numerical analysis to improve the reliability of the stacked PCB. The warpage of the interposer PCB decreased as the thermal expansion coefficient (CTE) of the prepreg decreased, and decreased as the glass transition temperature (Tg) increased. However, if temperature is 240℃ or higher, the reduction of warpage is not large. As FR-5 was applied, the warpage decreased more compared to FR-4, and the higher the number and thickness of the prepreg, the lower the warpage. For sub PCB, the CTE was more important for warpage than Tg of the prepreg, and increase in prepreg thickness was more effective in reducing the warpage. The shear tests indicated that the dummy pad design increased bonding strength. The tumble tests indicated that crack occurrence rate was greatly reduced with the dummy pad.