• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2C
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• pp.291-297
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• 2004

In this paper, a new structure for the AEC(Acoustic Echo Canceller) is proposed in which echo signal components that can be created in mobile communications is effectively eliminated. Block Data Flow Architecture is a parallel architecture that achieves high performance, high efficiency, high throughput, and almost linear speed up. The proposed architecture employs AEC and is implemented using the TMS320C6711 for real-time applications. The proposed AEC shows improved performance by eliminating echoes at 55ms delay path. Since the proposed AEC can also be implemented in Firmware, it is believed to effectively work on various types of echoes if it is applied on CDMA mobile devices. The TMS320C6711 shows much better performance comparing to previous DSPs. For experimental verifications, filtering operation using adaptive algorithm is performed on TMS320C6711 board and error signals resulted from computations are monitored on PC, and then the performance of the implemented AEC is verified through ERLE computation. According the results of simulation, good characteristic of 100dB are shown after 500 sampling data.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.3
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• pp.282-291
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• 2001

In this paper, an efficient VLSI architecture of Shape Adaptive Discrete Cosine Transform(SADCT) based on systolic array is proposed. Since transform size in SADCT is varied according to the shape of object in each block, it are dropped that both usability of processing elements(PE´s) and throughput rate in time-recursive SADCT structure. To overcome these disadvantages, it is proposed that the architecture based on a systolic way structure which doesn´t need memory. In the proposed architecture, throughput rate is improved by consecutive processing of one-dimensional SADCT without memory and PE´s in the first column are connected to that in the last one for improvement of usability of PE. And input data are put into each column of PE in parallel according to the maximum data number in each rearranged block. The proposed architecture is described by VHDL. Also, its function is evaluated by MentorTM. Even though the hardware complexity is somewhat increased, the throughput rate is improved about twofold.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2C
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• pp.49-58
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• 2005

For the improvement of coding efficiency, the H.264 standard uses new coding tools. Using these coding tools, H.264 has achieved significant improvements from rate-distortion point of view. The adoption of these tools enables a macroblock in H.264 to have more information, sixteen motion vectors, four reference frames and a macroblock mode. In this paper, we present an efficient temporal error concealment algorithm by using not only motion vectors and reference frames but also macroblock mode of neighbor macroblocks. Our algorithm conceals the macroblock error with variable sizes, $16{\times}16,\;16{\times}8,\;8{\times}16,\;8{\times}8$ depending on the macroblock modes of neighbor macroblocks. Simulation results show that the proposed method increase the objective quality regardless of bit-rate and block error rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.6A
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• pp.558-564
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• 2007

3G Long Term Evolution, which aims for various mobile multimedia service provision by enhanced wireless interface, proposes VoIP-based voice service through a Packet Switching (PS) domain. As delay and loss-sensitive VoIP traffic flows through the PS domain, more challenging technical difficulties are expected than in Circuit Switching (CS) domain based VoIP services. Moreover, since 3G LTE, which adopts the OFDM as its physical layer, introduces Physical Resource Block (PRB) as a unit for transmission resources, new types of resource management schemes are needed. This paper proposes a PRB scheduling algorithm of MAC layer for VoIP service in 3G LTE and shows the simulation results. The proposed algorithm has two key parts; dynamic activation of VoIP priority mode to satisfy VoIP QoS requirements and adaptive adjustment of the priority mode duration in order to minimize the degradation of resource utilization.

• Journal of Broadcast Engineering
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• v.23 no.2
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• pp.206-217
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• 2018

We develop the signal processing method for adaptive implementing direction of signal and the frequency sensitivity of human visual system(HVS). Existing multiband energy scaling method makes ringing artifact because it does not consider signal direction. To solve this problem, we use block gradient for signal direction in addition to existing method. And we use the fact that frequency component of signal is more sensitive than value of signal over human eyes. we enhance the signal according to contrast sensitivity function(CSF) which is the model of frequency sensitivity of human eye. Compared that the existing analysis models only improve the efficiencies in the existing systems, the developed method can process the image signals to be more desirable and suitable to HVS.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.543-545
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• 2017

This paper describes the SAO hardware architecture design for high performance in-loop filters. SAO is an inner module of in-loop filter, which compensates for information loss caused by block-based image compression and quantization. However, HEVC's SAO requires a high computation time because it performs pixel-unit operations. Therefore, the SAO hardware architecture proposed in this paper is based on a $4{\times}4$ block operation and a 2-stage pipeline structure for high-speed operation. The information generation and offset computation structure for SAO computation is designed in a parallel structure to minimize computation time. The proposed hardware architecture was designed with Verilog HDL and synthesized with TSMC chip process 130nm and 65nm cell library. The proposed hardware design achieved a maximum frequency of 476MHz yielding 163k gates and 312.5MHz yielding 193.6k gates on the 130nm and 65nm processes respectively.

• The Journal of the Korea Contents Association
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• v.18 no.12
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• pp.35-45
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• 2018

Motion Estimation(ME) has been developed to reduce the redundant data in digital video signal. ME is an important part of video encoding system, However, it requires huge computational complexity of the encoder part, and fast motion search methods have been proposed to reduce huge complexity. Multi- view video is obtained by capturing on a three-dimensional scene with many cameras at different positions and its complexity increases in proportion to the number of cameras. In this paper, we proposed an efficient motion method which chooses a search pattern adaptively by using the temporal-spatial correlation of the block and the characteristics of the block. Experiment results show that the computational complexity reduction of the proposed method over TZ search method and FS method can be up to 70~75% and 99% respectively while keeping similar image quality and bit rates.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.45-53
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• 2007

To recover transmitted signal perfectly at DTV receiver, we have to acquire carrier frequency synchronization to compensate pilot signal which located in wrong position and rotated phase. Also, we need a symbol timing synchronization to compensate sampling timing error. Conventionally, to synchronize symbol timing, we use Gardner's scheme which used in multi-level signal. Gardner's scheme is well known for its sampling the timing error signal from every symbol and it makes easy to detect and keep timing sync in multi-path channel. In this paper, to discuss the problem when the received power level is out of range and we cannot get synchronization information. With this problem, we use 2 step procedures. First, we put a received signal power compensation block before Garder's timing error detector. Second, adaptive loop filter to get a fast synchronization information and averaging loop filter's output value to reduce the amount of jitter after synchronization in PLL(Phased Locked Loop) circuit which is used to get a carrier frequency synchronization and symbol timing synchronization. Using the averaging value, we can estimate offset. Based on offset changing ratio, we can adapt adaptive loop filter to carrier frequency and symbol timing synchronization circuit.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.165-172
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• 2013

Convergence is increasingly prevalent in the IT world which generally refers to the combination of two or more different technologies in a single device. Especially, the spectrum scarcity is becoming a big issue because there are exponential growth of broadcasting and communication systems in the spectrum demand. Cognitive radio (CR) is a convergence technology that is envisaged to solve the problems in wireless networks resulting from the limited available spectrum and the inefficiency in the spectrum usage by exploiting the existing wireless spectrum opportunistically. However, the very process of convergence is likely to expose significant security issues due to the merging of what have been separate services and technologies and also as a result of the introduction of new technologies. The main purpose of this research is focused on devising an adaptive security framework based on carousel for CR networks as a distinct telecommunication convergence application, which are still at the stage of being developed and standardized with the lack of security concerns. The framework uses a secure credential, named as carousel, initialized with the location related information from objects position, which is used to design security mechanisms for supporting privacy and various securities based on it. The proposed adaptive security framework could be used as a security building block for the CR network standards and various convergence applications.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.4
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• pp.1830-1838
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• 2012

The intra prediction and the motion estimation of inter prediction occupy 70 ~ 80% of whole compression time in H.264/AVC. Compression efficiency has been higher, but complexity has increased and coding time has also increased much more. This paper proposes a block size decision method of the intra prediction and mode decision method which minimize the loss of video quality during the encoding and shorten the time spent. This paper, in addition, proposes an algorithm which determines the method of adaptive block mode for motion estimation of inter prediction. We investigated PSNR and the intra prediction and inter prediction of time-consuming calculations in order to measure video quality degradation and complexity through experiments. Consequently, when you use all three methods, these methods showed that average coding time is shortened as about 500 to 600ms in every frame in the case of all experimented videos, keeping video quality nearly similar, compared with existing methods of H.264.