• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.11
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• pp.3876-3895
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• 2014

Recently, Heterogeneous Network (HetNet) with Coordinated Multi-Point (CoMP) scheme is introduced into Long Term Evolution-Advanced (LTE-A) systems to improve digital services for User Equipments (UEs), especially for cell-edge UEs. However, Radio Resource Management (RRM), including Resource Block (RB) scheduling and Power Allocation (PA), in this scenario becomes challenging, due to the intercell cooperation. In this paper, we investigate the RRM problem for downlink transmission of HetNet system with Joint Processing (JP) CoMP (both joint transmission and dynamic cell selection schemes), aiming at maximizing weighted sum data rate under the constraints of both transmission power and backhaul capacity. First, joint RB scheduling and PA problem is formulated as a constrained Mixed Integer Programming (MIP) which is NP-hard. To simplify the formulation problem, we decompose it into two problems of RB scheduling and PA. For RB scheduling, we propose an algorithm with less computational complexity to achieve a suboptimal solution. Then, according to the obtained scheduling results, we present an iterative Karush-Kuhn-Tucker (KKT) method to solve the PA problem. Extensive simulations are conducted to verify the effectiveness and efficiency of the proposed algorithms. Two kinds of JP CoMP schemes are compared with a non-CoMP greedy scheme (max capacity scheme). Simulation results prove that the CoMP schemes with the proposed RRM algorithms dramatically enhance data rate of cell-edge UEs, thereby improving UEs' fairness of data rate. Also, it is shown that the proposed PA algorithms can decrease power consumption of transmission antennas without loss of transmission performance.

• The Journal of the Korea Contents Association
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• v.8 no.8
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• pp.47-56
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• 2008

MC(Mission Computer) performs important function in avionics system which tactic data processing, image processing and managing navigation system etc. In general, the fault of SPOF(Single Point Of Failure) in unity system can lead to failure of whole system. It can cause a failure of a mission and also can threaten to the life of the pilot. So, in this paper, we design the HA(Hight-availability) system so that dealing with the failure. And we use HA software like Heartbeat, Fake, DRBD and Bonding to manage HA system. Also we analyze the performance of HA system using the FDT(Fault Detection Time) for fast fault detection and MTTR(Mean Time To Repair) for mission continuity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1571-1578
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• 1999

In this paper, we present the Modulator Channel Card and VLSI chip for the Radio Transceiver Unit (RTU) of direct sequence code division multiple access (DS-CDMA) Wireless Local Loop (WLL) System. The Modulator Channel Card is designed and implemented using ASIC's, FPGA's and DSP's. The ASIC, compliance with Common Air Interface specification proposed by ETRI, has 40K gates which is designed to operate at 32MHz, and is fabricated using $0.6\mu\textrm{m}$ CMOS process. The ASIC carries out for I- or Q- phase data channel signal processing at a time, where each data channel processing consists of channel coding, block interleaving, scrambling, Walsh modulation, Pseudo-Noise (PN) spreading, and baseband filtering. The Modulator Channel Card has been integrated as a part of RTU of WLL system and is confirmed that it meets all functional and performance requirements.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10C
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• pp.961-967
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• 2009

In this paper, the lossless compression method is proposed for an 8-bit bitplane of the input image. The lower bitplanes are not well compressed because of irregularity of pixels. To overcome these drawbacks, this paper propose a mixed coding method that using the block-based lossless compression and the bit-based losselss compression, introducing the H. 264 and the JBIG. First, to take advantage of the characteristics of the bitplanes, 8-bitplane against the top 4 bits and lower 4 bits were separated. Next, the JBIG compression method was used in separated top 4-bitplane because of a lot of correlation between bits. And a separated lower 4-bitplane was applied the improved method that using the H. 264 lossless prediction. A pre-processing method applied to the lower 4-bitplane then irregular distribution of pixel values are converted to regular. Using the proposed method to test for various test images were performed. Experimental results from a printer using 8-bit image compared to JBIG average 19%, lower 4bit image compression performance with an average of 11% could be obtained.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.5 s.311
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• pp.48-56
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• 2006

In this paper, we proposed the high quality audio watermarking algorithm using MDCT/IMDCT (Modified DCT/Inverse Modified DCT) with psychoacoustic model. Generally, a digital audio watermark is embedding the frequency domain after frequency transform of the digital audio data but the digital audio quality is affected by watermarking. In our scheme, the digital audio data is spread with PN((Pseudo Noise) code and then audio watermark is embedded in MDCT processing that refers psychoacoustic model. In MDCT processing, according to the shape of filter bank output, the block switching selects a window sequence that has 256, 1,024 or 2,048 points interval for high quality audio. The author confirm that when watermark weight ${\alpha}$ is 2.5 below, the detection ratio of watermark is a satisfied to SDMI's(Secure Digital Music Initiative) recommendation 50% above and SM is $50{\sim}68dB$ range with mainly 4 kind of attacks(Compression, Cropping, FFT and Echo).

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.2
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• pp.345-352
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• 2017

In this paper, we design and implement an educational robot system that can use scratch education with the function of user demanding to perform robot education in actual school site in an embedded environment. It is developed to enable physical education for sensing information processing, software design and programming practice training that is the basis of robotic system. The development environment of the system is Arduino Uno based product using Atmega 328 core, debugging environment based on Arduino Sketch, firmware development language using C language, OS using Windows, Linux, Mac OS X. The system operation process receives the control command of the server using the Bluetooth communication, and drives various sensors of the educational robot. The curriculum includes Scratch program and Bluetooth communication, which enables real-time scratch training. It also provides smartphone apps and is designed to enable education like C and Python through expansion. Teachers at the school site used the developed products and presented performance processing results satisfying the missionary needs of the missionaries.

• The Transactions of the Korea Information Processing Society
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• v.4 no.3
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• pp.811-820
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• 1997

Disk arrays are using to enhance data trandfer rate and I/O performance in multimedia applications which need a high-performance storage device with large storage capacity and high-speed network.As performance varies with configuration and data layout scheme,disk array characteristic variables must be approrpriately deter-mined in desibning disk array archetecture for a speciffic applicatoin. In this paper,in order to design a disk array architecturte as a storage server of a small-scale VOD system,we evaluate performance of a disk array to chose the number of disks in the array,disk array cinfiguration,a degree of declustering for a given data block size of continous media file system and I/D request size through simulation.Simulation result shows that RAID level 5 with 5 disks ios a suitable candidate for the disk array architecture which privides MPEG-2 files with a rate of 6 Mbps,Moreover,we whow that stripe unit is 64 KB and a layout scheme is contigous placement.

• The Transactions of the Korea Information Processing Society
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• v.4 no.3
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• pp.821-830
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• 1997

The directory-based cache coherence scheme is an attractive approach to solve the caceh coherence problem in a large-scale shared-memory multiprocessor.However, the exsting directory-based schemes have some problens such as the enormous storage overhead for a directory, the long invalidation latency, the heavy network condes-tion, and the low scalability.For resolving these problems, we propose a new directroy- based caceh coherence scheme which is suitable for building scalable, shred-memory multiprocessors.In this scheme, each directory en-try ofr a given memory block is a number-balanced binaty tree(NBBT) stucture.The NBBT has several proper-ties to effciently maintain the directory for the cache consistency such that the shape is unique, the maximum depth is [log$_2$n], and the tree has the minimum number of leaf nodes among the binarry tree with n nodes.Therefore, this scheme can reduce the storage overhead, the network traffic, and the inbalidation latency and can ensutr the high- scalability the large-scale shared-memory multiprocessors.

• Journal of Digital Contents Society
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• v.14 no.1
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• pp.15-23
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• 2013

In response to the demands of large-scale data processing with low-power and new application, a storage system using SSD (Solid State Disk/Drive) with fast input-output performance instead of hard disc has appeared as storage device. Studies on methods to overcome specific problems of SSD such as various processing data units, out-place-update and limited delete count have been actively conducted. However, declining performance and stability have not been resolved yet when storing case specific data with small scale that causes frequent random write in hard disc or SSD. This thesis suggests a system structure that stores index requesting frequent random write in NVRAM capable of byte access by using characteristics such as byte unit fast read / write of NVRAM, non-volatile and smaller size of actual changed data size in index page than block size.