• The Journal of the Korea Contents Association
• /
• v.9 no.2
• /
• pp.1-9
• /
• 2009

In this paper, we propose the efficient processing technique for unavailable data in hardware implementation of motion estimator in H.264/AVC with parallel processing architecture. Motion estimation processing in the hardware is generally based on pipe-lining, some MV data of neighbor blocks are not available, whereas all MV data are valid in software processing where the data are sequentially processed. In this paper, we solve the problem of data being unavailable in MVp computation. To minimize the quality degradation caused by unavailable MVs, in the proposed method, the unavailable MV of a neighboring block is replaced with an integer pel unit MV, an MVp of neighboring blocks, or an MVcol (MV of co-located block). Comparing to the conventional method [7], our method outperformed maximally 0.832dB and 0.179dB for QCIF and CIF, respectively, in terms of BDPSNR.

• Proceedings of the Korea Institute of Convergence Signal Processing
• /
• 2000.12a
• /
• pp.93-96
• /
• 2000

In this paper, we suggest a feature points selection method using block-based watershed segmentation and polygon approximation for preprocessing of MPEG-4 mesh generation. 2D natural image is segmented by 8$\times$8 or 4$\times$4 block classification method and watershed algorithm. As this result, pixels on the watershed lines represent scene's interior feature and this lines are shapes of closed contour. Continuous pixels on the watershed lines are selected out feature points using Polygon approximation and post processing.

• Journal of The Korean Association of Information Education
• /
• v.26 no.3
• /
• pp.197-207
• /
• 2022

In this paper, we develop a machine learning based block code generation and recommendation model for the purpose of reducing cognitive load of learners during coding education that learns the learner's block that has been made in the block programming environment using natural processing model and fine-tuning and then generates and recommends the selectable blocks for the next step. To develop the model, the training dataset was produced by pre-processing 50 block codes that were on the popular block programming language web site 'Entry'. Also, after dividing the pre-processed blocks into training dataset, verification dataset and test dataset, we developed a model that generates block codes based on LSTM, Seq2Seq, and GPT-2 model. In the results of the performance evaluation of the developed model, GPT-2 showed a higher performance than the LSTM and Seq2Seq model in the BLEU and ROUGE scores which measure sentence similarity. The data results generated through the GPT-2 model, show that the performance was relatively similar in the BLEU and ROUGE scores except for the case where the number of blocks was 1 or 17.

• 제어로봇시스템학회:학술대회논문집
• /
• 2003.10a
• /
• pp.2641-2647
• /
• 2003

Conventional DLLs estimate the delay times of satellite signals individually and feed back these measurements to the VCO independently. But VDLL estimates delay times and user position directly and then estimate the feedback term for VCO using the estimated position changes. In this process, input measurements are treated as vectors and these vectors are used for navigation. First advantage of VDLL is that noise is reduced in all of the tracking channels making them less likely to enter the nonlinear region and fall below threshold. Second is that VDLL can operate successfully when the conventional independent parallel DLL approach fails completely. It means that VDLL receiver can get enough total signal power to track successfully to obtain accurate position estimates under the same conditions where the signal strength from each individual satellite is so low or week that none of the individual scalar DLL can remain in lock when operating independently. To operate VDLL successfully, it needs to know the initial user dynamics and position and prevents total system from the divergence. The suggested integration method is to use the inertial navigation system to provide initial dynamics for VDLL and to maintain total system stable. We designed the GPS/INS integrated navigation system. This new type of integrated system contained the vector pseudorange format generation block, VDLL signal processing block, position estimation block and the conversion block from position change to delay time feedback term aided by INS.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2011.05a
• /
• pp.6.1-6.1
• /
• 2011

Nanoscale block copolymer (BCP) patterns have been pursued for applications in sub-30 nm nanolithography. BCP self-assembly processing is scalable and low cost, and is well-suited for integration with existing semiconductor fabrication techniques. However, one of the major technical challenges for BCP self-assembly is limited tunability in pattern geometry, dimension, and functionality. We suggest methods for extending the degree of tunability by choosing highly incompatible polymer blocks and utilizing solvent vapor treatment techniques. Siloxane BCPs have been developed as self-assembling resists due to many advantages such as high etch-selectivity, good etch-resistance, long-range ordering, and reduced line-edge roughness. The large incompatibility leads to extensive degree of pattern tunability since the effective volume fraction can be easily manipulated by solvent-based treatment techniques. Thus, control of the microdomain size, periodicity, and morphology is possible by changing the vapor pressure and the mixing ratio of selective solvents. This allows a range of different pattern geometry such as dots, lines and holes and critical dimension simply by changing the processing conditions of a given block copolymer without changing a polymer chain length. We demonstrate highly extensive tunability (critical dimension ~6~30 nm) of self-assembled patterns prepared by a siloxane BCP with extreme incompatibility.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.05a
• /
• pp.404-406
• /
• 2015

This paper describes a small-area hardware implementation of the block cipher algorithm CLEFIA-128 which supports for 128-bit master key. A compact structure using single data processing block is adopted, which shares hardware resources for round transformation and the generation of intermediate values for round key scheduling. In addition, data processing and key scheduling blocks are simplified by utilizing a modified GFN(generalized Feistel network) and key scheduling scheme. The CLEFIA-128 crypto-processor is verified by FPGA implementation. It consumes 823 slices of Virtex5 XC5VSX50T device and the estimated throughput is about 105 Mbps with 145 MHz clock frequency.

• The Transactions of the Korea Information Processing Society
• /
• v.3 no.5
• /
• pp.1329-1336
• /
• 1996

In many image compression applications, the discrete cosine transform (DCY) is well known for is highly efficient coding performance. However, it produces undesirable block artifacts in low-bit rate coding. In addition, in many practical applications, faster computation and easier VLST implementation of DCT coefficients are also important issues. The removal of the block artifacts and faster DCT computation are therefor of practical interest. In this paper, a modified DCTcomputation scheme was investigated, which provides a simple efficient solution to the reduction of the block artifacts while achieving faster computation. We have applied the new ap-proach to the low-bit rate coding and decoding of images. Simulation results on real images have verified the improved performance of the proposed method over the standar d method.

• Proceedings of the IEEK Conference
• /
• 2002.07b
• /
• pp.1296-1299
• /
• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2005.11a
• /
• pp.263-266
• /
• 2005

실시간 시스템은 시간적 정확성을 갖기 때문에 소형 임베디드 시스템부터 대형 분산 시스템까지 많은 분야에서 사용되고 실시간 시스템을 기반으로 하는 실시간 프로그램도 많은 분야에서 사용되고 있다. 이러한 실시간 프로그램의 시간적 특성을 지키기 위해 개발자들은 프로그램 개발에 집중하지 못하고 실행시간의 정의와 정의한 실행시간의 정확성 검사에 많은 시간을 보내고 있다. 실시간 시스템에 대한 연구 결과로서 TMO 모델은 실시간 개념에 따른 시간 처리의 다양한 기능을 지원하고, 응답시간을 보장하여 개발자가 프로그램 개발에 집중할 수 있다. 하지만, 실행시간의 정의는 개발자에 의해 이루어지기 때문에 이를 정의하고 그 정확성 여부를 확인하는 작업은 어렵다. 이러한 문제로 인하여 실행시간 정의의 기준점을 제시할 수 있는 도구가 필요하지만 이를 위한 TMO 분석 도구에 대한 연구는 미흡하다. 이에 본 논문에서는 TMO 기반 정적 분석 도구를 위한 PS-Block을 제시한다. PS-Block은 블록 단위로 실행시간을 분석할 수 있는 기반으로써 프로그램을 작업 단위로 분리하여 분석할 수 있도록 한다. 이를 기반으로 실행시간을 분석하여 시간 정보 결정의 기준으로 하고, 실시간 메소드의 적시성 확인을 쉽게 함으로써 실시간/신뢰성의 향상과 개발 기간을 단축할 수 있다.

• Journal of Institute of Control, Robotics and Systems
• /
• v.12 no.7
• /
• pp.706-712
• /
• 2006

Recursive Partial Least Squares(RPLS) method has been used for processing the on-line available multivariate chemical process data and modeling adaptive prediction model for process changes. However, RPLS method is unstable in PLS model updating because RPLS method updates PLS model by merging past PLS model and new data. In this study, Adaptive Predictive Partial Least Squres(APPLS) method is suggested for more sensitive adaptation to process changes. By expanding APPLS method, block-wise Adaptive Predictive Partial Least Squares(block-wise APPLS) method is suggested for a lager scale data of chemical processes. APPLS method has been applied to predict the reactor properties and the product quality of a direct esterification reactor for polyethylene terephthalate(PTT), and block-wise APPLS method has been applied to predict the cetane number using NIR Diesel Spectra data. APPLS and block-wise APPLS methods show better prediction and updating performance than RPLS method.