• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.3 no.2
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• pp.58-63
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• 2010

Cryptography is primarily a computationally intensive process. In this paper we expand AES scheme for analysis of computation time with four criteria, first is the compression of plain data, second is the variable size of block, third is the selectable round, fourth is the selective function of whole routine. We have tested our encryption scheme by c++ using MinGW GCC. Through extensive experimentations of our scheme we found that the optimal block size.

• Journal of Korea Multimedia Society
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• v.7 no.12
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• pp.1719-1728
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• 2004

The fusion of Internet technology and applications with wireless communication provides a new business model and promises to extend the possibilities of commerce to what is popularly called mobile commerce, or m-commerce. In mobile Internet banking service through wireless local area network, security is a most important factor to consider. We describe the development of security service for mobile Internet banking on Personal Digital Assistants (PDAs). Banking Server and Authentication Server were developed to simulate banking business and to support certificate management of authorized clients, respectively. To increase security, we took hybrid approach in implementation: symmetric block encryption and public-key encryption. Hash function and random number generation were exploited to generate a secret key. The data regarding banking service were encrypted with symmetric block encryption, RC4, and the random number sequence was done with public-key encryption. PDAs communicate through IEEE 802.IIb wireless LAN (Local Area Network) to access banking service. Several banking services and graphic user interfaces, which emulatedthe services of real bank, were developed to verity the working of each security service in PDA, the Banking Server, and the Authentication Server.

• Journal of the Korea Computer Industry Society
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• v.10 no.4
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• pp.167-176
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• 2009

In this paper, we propose an improved SHACAL-1 of the same encryption and decryption with a simple symmetric layer. SHACAL-1 has 4 rounds, and each round has 20 steps. Decryption is becoming inverse function of encryption, In this paper, we proposed SHACAL-1 are composed of the first half, symmetry layer and the last half. The first half with SHACAL-1 encryption algorithm 1 round does with 10 steps and composes of 4 round. The last half identically with SHACAL-1 decryption algorithm, has a structure. On the center inserts a symmetry layer, encryption and decryption algorithm identically, composes. In the experiments, the proposed SHACAL-1 algorithm showed similar execution time to that of the SHACAL-1. Thanks to the symmetric layer, the proposed algorithm makes it difficult for the attacks which take advantages of high probability path such as the linear cryptanalysis, differential cryptanalysis. The proposed algorithm can be applicable to the other block cipher algorithms which have different encryption and decryption and useful for designing a new block cipher algorithm.

• Journal of IKEEE
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• v.22 no.1
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• pp.104-109
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• 2018

This paper presents a hardware design for the block encryption algorithm of ARIA which is used for standard in Korea. It presents a hardware-efficient design to increase the throughput for the ARIA algorithm using a high-speed pipeline architecture. We have used ROM for the S-box implementation. This approach aims to decrease the critical path delay of the encryption. In this paper, hardware was designed by VHDL, realized RTL level by Synplify which is synthesis tool and verified simulation by ModelSim. The ARIA algorithm is shown 68.3 MHz (Maximum operation frequency) to use Xilinx VertxE XCV Series device.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.12
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• pp.4508-4530
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• 2021

Today distributed data storage service are being widely used. However lack of proper means of security makes the user data vulnerable. In this work, we propose a Randomized Block Size (RBS) model for secure data storage in distributed environments. The model work with multifold block sizes encrypted with the Chinese Remainder Theorem-based RSA (C-RSA) technique for end-to-end security of multimedia data. The proposed RBS model has a key generation phase (KGP) for constructing asymmetric keys, and a rand generation phase (RGP) for applying optimal asymmetric encryption padding (OAEP) to the original message. The experimental results obtained with text and image files show that the post encryption file size is not much affected, and data is efficiently encrypted while storing at the distributed storage server (DSS). The parameters such as ciphertext size, encryption time, and throughput have been considered for performance evaluation, whereas statistical analysis like similarity measurement, correlation coefficient, histogram, and entropy analysis uses to check image pixels deviation. The number of pixels change rate (NPCR) and unified averaged changed intensity (UACI) were used to check the strength of the proposed encryption technique. The proposed model is robust with high resilience against eavesdropping, insider attack, and chosen-plaintext attack.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.3
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• pp.427-433
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• 2002

This paper describes a design of cryptographic processor that implements the AES(Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation, the round block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.-V supply.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.3 s.309
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• pp.10-19
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• 2006

In this paper, we propose 128-bit chaotic block encryption scheme using a PLCM(Piecewise Linear Chaotic Map) having a good dynamical property. The proposed scheme has a block size of 12n-bit and a key size of 125-bit. The encrypted code is generated from the output of PLCM. We show the proposed scheme is very secure against statistical attacks and have very good avalanche effect and randomness properties.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.777-779
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• 2014

The LEA(Lightweight Encryption Algorithm) is a 128-bit high-speed/lightweight block cipher algorithm developed by National Security Research Institute(NSRI) in 2012. The LEA encrypts plain text of 128-bit using cipher key of 128/192/256-bit, and produces cipher text of 128-bit, and vice versa. To reduce hardware complexity, we propose an efficient architecture which shares hardware resources for encryption and decryption in round transformation block. Hardware sharing technique for key scheduler was also devised to achieve area-efficient and low-power implementation. The designed LEA cryptographic processor was verified by using FPGA implementation.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.136-139
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• 2000

In this paper, we propose a prime code and a new cryptographic algorithm for encryption and decryption as its application. The characteristics of prime numbers with irregular distribution and uniqueness are used to generate the prime code. Based on the prime code, an encryption algorithm for secret key is presented. Since the algorithm requires simpler operations than existing encryption such as DES, the burden for hardware implementation of the encryption and decryption process is alleviated.

• ETRI Journal
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• v.33 no.6
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• pp.935-944
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• 2011

As a growing number of individuals are exposed to surveillance cameras, the need to prevent captured videos from being used inappropriately has increased. Privacy-related information can be protected through video encryption during transmission or storage, and several algorithms have been proposed for such purposes. However, the simple way of evaluating the security by counting the number of brute-force trials is not proper for measuring the security of video encryption algorithms, considering that attackers can devise specially crafted attacks for specific purposes by exploiting the characteristics of the target video codec. In this paper, we introduce a new attack for recovering contour information from encrypted H.264 video. The attack can thus be used to extract face outlines for the purpose of personal identification. We analyze the security of previous video encryption schemes against the proposed attack and show that the security of these schemes is lower than expected in terms of privacy protection. To enhance security, an advanced block shuffling method is proposed, an analysis of which shows that it is more secure than the previous method and can be an improvement against the proposed attack.