• Journal of Internet Computing and Services
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• v.18 no.5
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• pp.1-8
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• 2017

Lightweight Encryption Algorithm(LEA) was developed by National Security Research Institute(NSRI) in 2013 and targeted to be suitable for environments for big data processing, cloud service, and mobile. LEA specifies the 128-bit message block size and 128-, 192-, and 256-bit key sizes. In this paper, block cipher LEA algorithm which can encrypt and decrypt 128-bit messages is designed using Verilog-HDL. The designed IP for encryption and decryption has a maximum throughput of 874Mbps in 128-bit key mode and that of 749Mbps in 192 and 656Mbps in 256-bit key modes on Xilinx Vertex5. The cryptographic IP of this paper is applicable as security module of the mobile areas such as smart card, internet banking, e-commerce and IoT.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.159-167
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• 2006

Lipreading has been suggested as one of the methods to improve the performance of speech recognition in noisy environment. However, existing methods are developed and implemented only in software. This paper suggests a hardware design for real-time lipreading. For real-time processing and feasible implementation, we decompose the lipreading system into three parts; image acquisition module, feature vector extraction module, and recognition module. Image acquisition module capture input image by using CMOS image sensor. The feature vector extraction module extracts feature vector from the input image by using parallel block matching algorithm. The parallel block matching algorithm is coded and simulated for FPGA circuit. Recognition module uses HMM based recognition algorithm. The recognition algorithm is coded and simulated by using DSP chip. The simulation results show that a real-time lipreading system can be implemented in hardware.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.4
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• pp.265-269
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• 2009

A conference key agreement system is a scheme to generate a session key in a contributory manner in order to communicate with each other securely among participants. In this paper an efficient conference key agreement system is proposed by employing symmetric balanced incomplete block design(SBIBD), one class of block designs. The protocol presented not only minimizes the message overhead and message exchanging rounds but also makes every participant contribute evenly for generating a conference key. Our protocol constructs a conference key which takes modified Diffe-Helman form of ${\prod}_{i=0}^{v-1}R_i$, where v is the number of participants and $R_i$ is a random number generated from member i. In a special class of SBIBD, it takes only 3 rounds message exchange and message overhead is $O(v{\sqrt{v}})$. Our protocol can be proved as computationally difficult to calculate as discrete logarithms.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.2
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• pp.313-318
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• 2020

Since the engineering plastics having a melting point of higher than 300 degrees have a high mechanical rigidity, chemical resistance, friction and abrasion performance, those are being highlighted as metal replacement materials in various industries. In this study, 3D printer nozzle with excellent heat dissipation characteristics are designed and analytically verified to form engineering plastics with high melting points in 3D printers based on the melt-lamination modeling method. In order to insulate between the heat block heated to a melting point of filament material and the upper part of the nozzle where the filament is transferred, the heat brake part with low thermal conductivity was designed to have two separate parts, and a cooling fin structure is further applied to the heat brake part to lower steady-state temperature by air convection. Optimized structural design on FDM nozzle part reduces the temperature at the heat sink and at the end part of heat brake by 50% and 14% respectively, compared to the conventional BCnozzle structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.29-36
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• 2003

In this paper, an efficient VLSI architecture for DCTQ module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the module is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling 30 frame CIF image for both encoder and decoder simultaneously. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. To reduce the power consumption of DCTQ modu1e, we propose the method not to operate the DCTQ modu1e exploiting the SAE(sum of absolute error) value from motion estimation and cbp(coded block pattern). To reduce the AC/DC prediction memory size, the memory architecture and memory access method for AC/DC prediction block is proposed. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.

• Journal of Korea Water Resources Association
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• v.45 no.7
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• pp.675-684
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• 2012

Recently, a heavy rainfall under climate change causes the flood exceeded river's conveyance. Flood control methods under the limited river width are the increase of embankment, the construction of storage pockets and diversion channel, the dredging of river bed. Hwasun flood control reservoir of washland is designed as the storage pockets and the regulating gate for the control of water level. In this study, the propriety of design was investigated through hydraulic experiments for the circumstances to exclude the constant flood discharge during operation period. In the results, the over flow rate of side weir exceeded the flow of design and indicated to be able to discharge the designed flow in the regulating gate opened 1.1 m. The high velocity 7.1 m/s behind the gate has investigated to reduce under 3.3 m/s by the baffle block.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.20-25
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• 2005

A high performance Viterbi decoder is designed using modified register exchange scheme and block decoding method. The elimination of the trace-back operation reduces the operation cycles to determine the merging state and the amount of memory. The Viterbi decoder has low latency, efficient memory organization, and low hardware complexity compared with other Viterbi decoding methods in block decoding architectures. The elimination of trace-back also reduces the power consumption for finding the merging state and the access to the memory. The proposed decoder can be designed with emphasis on either efficient memory or low latency. Also, it has a scalable structure so that the complexity of the hardware and the throughput are adjusted by changing a few design parameters before synthesis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.10A
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• pp.809-815
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• 2011

In this paper, we have proposed and implemented a novel architecture which can be used to effectively design the modified Euclidean (ME) algorithm for key equation solver (KES) block in high-speed Reed-Solomon (RS) decoder. With polynomial expressions of newly-defined state variables for controlling each processing element (PE), the proposed architecture has simple input/output signals and requires less hardware complexity because no degree computation circuits are needed. In addition, since each PE circuit is independent of the error correcting capability t of RS codes, it has the advantage of linearly increase of the hardware complexity of KES block as t increases. For comparisons, KES block for RS(255,239,8) decoder is implemented using Verilog HDL and synthesized with 0.13um CMOS cell library. From the results, we can see that the proposed architecture can be used for a high-speed RS decoder with less gate count.

• Journal of the Korea institute for structural maintenance and inspection
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• v.14 no.2
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• pp.97-105
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• 2010

The displacements of steel deck bridge due to construction step are measured, and three dimensional analysis with full modeling is carried out to compare with the measured results. Three dimensional structural analyses considering construction step by large block construction method are accomplished with verified model. The conclusions are as follows. 1. Comparing the data of grid analysis with the result of 3D full modeling in steel deck bridge, the design method using grid analysis has a limit for describing the displacements of curved bridge. The analysis of 3D full modeling has been proved as more accurate method. The differentiation of results in two methods is about 10%~20%. 2. It is verified that the maximum displacement of during construction is 1.7 times larger than the displacement of final construction. 3. The bridge behavior considering the construction step is somewhat different from that of final stage in whole structure and the displacement and stress during construction is larger than that of final construction. Therefore, it needs the reasonable structural design considering the construction step to get economical efficiency and a high competitive construction.

• Journal of the Architectural Institute of Korea Structure & Construction
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• v.35 no.5
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• pp.169-179
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• 2019

During the initial design stage of apartment complex, the photovoltaic(PV) system has been considered as an alternative of renewable energy system and planned to install at the rooftop floor level in general. The electric power generation characteristics can be influenced by the block layout, building orientation and roof top structure because of azimuth angle, tilt angle, and partial shading. This study aims to investigate power generation characteristics of photovoltaic system in apartment buildings by considering the partial shading conditions due to the block layout, building orientation and roof-top structures. For the photovoltaic module arrangement planning in rooftop floor level, shading areas were firstly analyzed due to the adjacent building structure. And the annual and seasonal power generation of PV system were analyzed through the PVsyst simulation results. The results show that shading period at the roof top surface can be increased due to the parapet and water tank. Initial design power capacity can be decreased by considering the daily insolation period and distance between PV modules through the shading simulation. As the number of PV modules decreases, the annual power generation can be decreased. However annual power generation per unit area of PV modules can be increased and performance ratio can be increased above 80%. Also the power generation of PV system can be critically affected by building orientation and the performance ratio can be drastically decreased in east-oriented buildings due to the shading problems caused by adjacent structures at roof top level such as parapet and water tank.