• Title/Summary/Keyword: block design

Search Result 3,013, Processing Time 0.034 seconds

10Gbps Driver Design with Pre-Emphasis Functionality (Pre-Emphasis 기능을 갖는 10Gbps 드라이버의 설계)

  • Lee, Woo-Kwan;Rim, Woo-Jin;Kim, Soo-Won
    • Proceedings of the IEEK Conference
    • /
    • 2005.11a
    • /
    • pp.691-694
    • /
    • 2005
  • This paper proposed 10Gbps driver with pre-emphasis for high speed transmitter. the proposed driver increase bandwidth using Ft doubler method and design driver block and pre-emphasis block in together. Pre-emphasis functionality confirmed to control VDS of current source o driver, not to control slew rate of termination resistor. The proposed driver is designed in a 1.5V/0.13um 1-poly, 5-metal CMOS mixed-signal process.

  • PDF

A study on material selection for semiconductor die parts and on their modification and manufacture (반도체금형에서 부속부품의 재료선정 및 개선과 제작에 관한 연구)

  • Kim, Sei-hwan;Choi, Kye-kwang
    • Design & Manufacturing
    • /
    • v.8 no.1
    • /
    • pp.27-30
    • /
    • 2014
  • Alloy tool steel such as SKD11 and SKD61 or high speed tool like SKH51 are used as materials for semiconductor dies. Cavities, curl blocks, pot blocks and housings are made from those materials. To make those parts from alloy tool steel or high speed tool, one utilizes discharge machining, and mechanical machining including machining center, milling, drilling, forming grinding and others. In the process of cutting machining and polishing, the die materials become unsuitable for machining owing to bubbles and foreign substances in them, which hinders production process. Therefore, this study focuses on die material selection criteria, and on analysis and comparison of material characteristics to help companies to solve their problems, make die manufacture less burdensome and extend die life.

  • PDF

Design of a Block Data Flow Architecture for 2-D DWT/IDWT (2차원 DWT/IDWT의 블록 데이터 플로우 구조 설계)

  • 정갑천;강준우
    • Proceedings of the IEEK Conference
    • /
    • 1998.10a
    • /
    • pp.1157-1160
    • /
    • 1998
  • This paper describes the design of a block data flow architecture(BDFA) which implements 2-D discrete wavelet transform(DWT)/inverse discrete wavelet transform(IDWT) for real time image processing applications. The BDFA uses 2-D product separable filters for DWT/IDWT. It consists of an input module, a processor array, and an output module. It use both data partitioning and algorithm partitioning to achieve high efficiency and high throughput. The 2-D DWT/IDWT algorithm for 256$\times$256 lenna image has been simulated using IDL(Interactive Data Language). The 2-D array structured BDFA for the 2-D filter has been modeled and simulated using VHDL.

  • PDF

The Design of unevenly leaf width distributed Multileaf Collimator (불균일 폭 분포를 갖는 Multileaf Collimator 설계에 관한 연구)

  • 이병용;장혜숙;조병철
    • Progress in Medical Physics
    • /
    • v.5 no.2
    • /
    • pp.45-48
    • /
    • 1994
  • We have studied about leaf-width distribution of Multileaf Collimator(MLC). We have analyzed 1169 treatment fields from 303 patients who have treated by radiation therapy. From this analysis, we can design an unevenly leaf-width distributed MLC, by placing the smaller leaf widths for more frequent blocking region and the larger for less. The average width of total leaves is 0.8 cm, but the effective block width is 0.5-0.6 cm for frequently blocking region(3-6 cm from the field center).

  • PDF

Design of BIST Circuits for Test Algorithms Using VHDL (VHDL을 이용한 테스트 알고리즘의 BIST 회로 설계)

  • 배성환;신상근;김대익;이창기;전병실
    • The Journal of the Acoustical Society of Korea
    • /
    • v.18 no.1
    • /
    • pp.67-71
    • /
    • 1999
  • In this paper, we design circuits embedded in memory chip which perform memory testing algorithms using BIST scheme to reduce testing time and cost for testing. In order to implement circuits for MSCAN, Marching and checkerboard test algorithms, which have widely used in memory testing, we survey structure of the BIST circuits and describe each block of BIST circuits by using VHDL. Thereafter, We verify behavior of each VHDL coding block and extract BIST circuits for target testing algorithms by CAD tool for simulation and synthesis. Extracted circuits have very low area overhead.

  • PDF

Research Needs for TSV-Based 3D IC Architectural Floorplanning

  • Lim, Sung Kyu
    • Journal of information and communication convergence engineering
    • /
    • v.12 no.1
    • /
    • pp.46-52
    • /
    • 2014
  • This article presents key research needs in three-dimensional integrated circuit (3D IC) architectural floorplanning. Architectural floorplaning is done at a very early stage of 3D IC design process, where the goal is to quickly evaluate architectural designs described in register-transfer level (RTL) in terms of power, performance, and reliability. This evaluation is then fed back to architects for further improvement and/or modifications needed to meet the target constraints. We discuss the details of the following research needs in this article: block-level modeling, through-silicon-via (TSV) insertion and management, and chip/package co-evaluation. The goal of block-level modeling is to obtain physical, power, performance, and reliability information of architectural blocks. We then assemble the blocks into multiple tiers while connecting them using TSVs that are placed in between hard IPs and inside soft IPs. Once a full-stack 3D floorplanning is obtained, we evaluate it so that the feedback is provided back to architects.

A Graphical Method for Evaluating the Effect of Blocking in Response surface Designs Using Cuboidal Regions

  • Sang-Hyun Park;Dae-Heung Jang
    • Communications for Statistical Applications and Methods
    • /
    • v.5 no.3
    • /
    • pp.607-621
    • /
    • 1998
  • When fitting a response surface model, the least squares estimates of the model's parameters and the prediction variance will generally depend on how the response surface design is blocked. That is, the choice of a blocking arrangement for a response surface design can have a considerable effect on estimating the mean response and on the size of the prediction variance even if the experimental runs are the same. Therefore, care should be exercised in the selection of blocks. In this paper, we prognose a graphical method for evaluating the effect of blocking in a response surface designs using cuboidal regions in the presence of a fixed block effect. This graphical method can be used to investigate how the blocking has influence on the prediction variance throughout the entire experimental region of interest when this region is cuboidal, and compare the block effect in the cases of the orthogonal and non-orthogonalblockdesigns, resfectively.

  • PDF

Various Thermodynamic Factors in Designing Nanostructured Materials from Block Copolymers

  • Cho, Jun-Han
    • Proceedings of the Polymer Society of Korea Conference
    • /
    • 2006.10a
    • /
    • pp.207-208
    • /
    • 2006
  • Here, we discuss various thermodynamic factors that affect the design of nanomaterials based on block copolymers. It is well known that the ordering behavior is determined by composition, chain size N, and the ubiquitous Flory. However, the recent discovery of ordering upon heating, immisibility loops, and baroplasticity addresses a clear need for further microscopic interpretation of such. in order to help to design nanomaterials at aimed purposes. Employing a perturbed hard sphere chain model, the molecular factors such as self and cross-interactions, free space distribution, and directional interactions are incorporated in. It is shown that not only typical ordering phenomena, but also the recent observations just mentioned are all described through this unified way.

  • PDF

Output feedback model predictive control for Wiener model with parameter dependent Lyapunov function

  • Yoo, Woo-Jong;Ji, Dae-Hyun;Lee, Sang-Moon;Won, Sang-Chul
    • 제어로봇시스템학회:학술대회논문집
    • /
    • 2005.06a
    • /
    • pp.685-689
    • /
    • 2005
  • In this paper, we consider a robust output feedback model predictive controller(MPC) design for Wiener model. Nonlinearities that couldn't be represented in static nonlinearity block of Wiener model are regarded as uncertainties in linear block. An dynamic output feedback controller design method is presented for Wiener MPC. According to MPC algorithm, the control law is computed based on linear matrix inequality(LMI)at each sampling time by solving convex optimization. Also, a new parameter dependent Lyapunov function is proposed to get a less conservative condition. The results are illustrated with numerical example.

  • PDF

An Experimental Study on Concrete Stress Distribution in Compression Zone (콘크리트 압축 응력분포에 관한 실험적 연구)

  • Lee, Jae-Hoon;Lim, Kang-Sup;Choi, Jin-Ho;Choi, Young-Ho;Hwang, Do-Kyu;Yoo, Hyun-Jae
    • Proceedings of the Korea Concrete Institute Conference
    • /
    • 2009.05a
    • /
    • pp.79-80
    • /
    • 2009
  • Compression stress distribution used to concrete structure design substitutes equivalent rectangle, trapezoid and parabola-rectangle stress block for actual concrete stress distribution. Presently, rectangular stress block of Korea Concrete Design Code is equal to it of ACI code that doesn't reflect the material feature of the high strength concrete. The study does an experiment on concrete compression stress distribution to know the material feature of the concrete used in korea.

  • PDF