• Title/Summary/Keyword: bit mask

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Audio fingerprint matching based on a power weight (파워 가중치를 이용한 오디오 핑거프린트 정합)

  • Seo, Jin Soo;Kim, Junghyun;Kim, Hyemi
    • The Journal of the Acoustical Society of Korea
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    • v.38 no.6
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    • pp.716-723
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    • 2019
  • Fingerprint matching accuracy is essential in deploying a music search service. This paper deals with a method to improve fingerprint matching accuracy by utilizing an auxiliary information which is called power weight. Power weight is an expected robustness of each hash bit. While the previous power mask binarizes the expected robustness into strong and weak bits, the proposed method utilizes a real-valued function of the expected robustness as weights for fingerprint matching. As a countermeasure to the increased storage cost, we propose a compression method for the power weight which has strong temporal correlation. Experiments on the publicly-available music datasets confirmed that the proposed power weight is effective in improving fingerprint matching performance.

Design of a Large-density MTP IP (대용량 MTP IP 설계)

  • Kim, YoungHee;Ha, Yoon-Kyu;Jin, Hongzhou;Kim, SuJin;Kim, SeungGuk;Jung, InChul;Ha, PanBong;Park, Seungyeop
    • Journal of IKEEE
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    • v.24 no.1
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    • pp.161-169
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    • 2020
  • In order to reduce the manufacturing cost of MCU chips used in applications such as wireless chargers and USB-C, compared to DP-EEPROM (Double Poly EEPROM), which requires 3 to 5 additional process masks, it is even more necessary MTP(Multi-Time Programmable), which is less than one additional mask and have smaller unit cell size. In addition, in order to improve endurance characteristics and data retention characteristics of the MTP memory cell due to E/P(Erase / Program) cycling, the distribution of the VTP(Program Threshold Voltage) and the VTE(Erase Threshold Voltage) needs to be narrow. In this paper, we proposed a current-type BL S/A(Bit-Line Sense Amplifier) circuit, WM(Write Mask) circuit, BLD(BL Driver) circuit and a algorithm, which can reduce the distribution of program and VT and erase VT, through compare the target current by performing the erase and program pulse of the short pulse several times, and if the current specification is satisfied, the program or erase operation is no longer performed. It was confirmed that the 256Kb MTP memory fabricated in the Magnachip semiconductor 0.13㎛ process operates well on the wafer in accordance with the operation mode.

A Study on Local Micro Pattern for Facial Expression Recognition (얼굴 표정 인식을 위한 지역 미세 패턴 기술에 관한 연구)

  • Jung, Woong Kyung;Cho, Young Tak;Ahn, Yong Hak;Chae, Ok Sam
    • Convergence Security Journal
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    • v.14 no.5
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    • pp.17-24
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    • 2014
  • This study proposed LDP (Local Directional Pattern) as a new local micro pattern for facial expression recognition to solve noise sensitive problem of LBP (Local Binary Pattern). The proposed method extracts 8-directional components using $m{\times}m$ mask to solve LBP's problem and choose biggest k components, each chosen component marked with 1 as a bit, otherwise 0. Finally, generates a pattern code with bit sequence as 8-directional components. The result shows better performance of rotation and noise adaptation. Also, a new local facial feature can be developed to present both PFF (permanent Facial Feature) and TFF (Transient Facial Feature) based on the proposed method.

A study on implementation of optical high-speed multiplier using multiplier bit-pair recoding derived from Booth algorithm (Booth 알고리즘의 승수 비트-쌍 재코딩을 이용한 광곱셈기의 구현에 관한 연구)

  • 조웅호;김종윤;노덕수;김수중
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.10
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    • pp.107-115
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    • 1998
  • A multiplier bit-pair recoding technique derived from Booth algorithm is used as an effective method that can carry out a fast binary multiplication regardless of a sign of both multiplicand and multiplier. In this paper, we propose an implementation of an optical high-speed multiplier which consists of a symbolic substitution adder and an optical multiplication algorithm, which transforms and enhances the multiplier bit-pair recoding algorithm to be fit for optical characteristics. Specially, a symbolic substitution addition rules are coded with a dual-rail logic, and so the complement of the logic of the symbolic substitution adder is easily obtained with a shift operation because it is always present. We also construct the symbolic substitution system which makes superposition image by superimposing two shifted images in a serial connection and recognizes a reference image by feeding this superimposed image to a mask. Thus, the optical multiplier, which is compared with a typical system, is implemented to the smaller system by reducing the number of optical passive elements and the size of this system.

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Accelerated Convolution Image Processing by Using Look-Up Table and Overlap Region Buffering Method (Loop-Up Table과 필터 중첩영역 버퍼링 기법을 이용한 컨벌루션 영상처리 고속화)

  • Kim, Hyun-Woo;Kim, Min-Young
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.49 no.4
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    • pp.17-22
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    • 2012
  • Convolution filtering methods have been widely applied to various digital signal processing fields for image blurring, sharpening, edge detection, and noise reduction, etc. According to their application purpose, the filter mask size or shape and the mask value are selected in advance, and the designed filter is applied to input image for the convolution processing. In this paper, we proposed an image processing acceleration method for the convolution processing by using two-dimensional Look-up table (LUT) and overlap-region buffering technique. First, based on the fixed convolution mask value, the multiplication operation between 8 or 10 bit pixel values of the input image and the filter mask values is performed a priori, and the results memorized in LUT are referred during the convolution process. Second, based on symmetric structural characteristics of the convolution filters, inherent duplicated operation region is analysed, and the saved operation results in one step before in the predefined memory buffer is recalled and reused in current operation step. Through this buffering, unnecessary repeated filter operation on the same regions is minimized in sequential manner. As the proposed algorithms minimize the computational amount needed for the convolution operation, they work well under the operation environments utilizing embedded systems with limited computational resources or the environments of utilizing general personnel computers. A series of experiments under various situations verifies the effectiveness and usefulness of the proposed methods.

Novel Spectrally Efficient UWB Pulses Using Zinc and Frequency-Domain Walsh Basis Functions

  • Chaurasiya, Praveen;Ashrafi, Ashkan;Nagaraj, Santosh
    • ETRI Journal
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    • v.35 no.3
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    • pp.397-405
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    • 2013
  • In this paper, two sets of spectrally efficient ultra-wideband (UWB) pulses using zinc and frequency-domain Walsh basis functions are proposed. These signals comply with the Federal Communications Commission (FCC) regulations for UWB indoor communications within the stipulated bandwidth of 3.1 GHz to 10.6 GHz. They also demonstrate high energy spectral efficiency by conforming more closely to the FCC mask than other UWB signals described in the literature. The performance of these pulses under various modulation techniques is discussed in this paper, and the proposed pulses are compared with Gaussian monocycles in terms of spectral efficiency, autocorrelation, crosscorrelation, and bit error rate performance.

Feature Extraction Techniques from Micro Drill Bits Images (마이크로 드릴 비트 영상에서의 특징 추출 기법)

  • Oh, Se-Jun;Kim, Nak-Hyun
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.919-920
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    • 2008
  • In this paper, we present early processing techniques for visual inspection of metallic parts. Since metallic surfaces give rise to specular reflections, it is difficult to extract object boundaries using elementary segmentation techniques such as edge detection or binary thresholding. In this paper, we present two techniques for finding object boundaries on micro bit images. First, we explain a technique for detecting blade boundaries using a directional correlation mask. Second, a line and angle extraction technique based on Harris corner detector and Hough transform is described. These techniques have been effective for detecting blade boundaries, and a number of experimental results are presented using real images.

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Simulation of HTS RSFQ A/D Converter and its Layout (고온 초전도 RSFQ A/D 변환기의 시물레이션과 설계)

  • 남두우;정구락;강준희
    • Progress in Superconductivity and Cryogenics
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    • v.4 no.1
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    • pp.8-12
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    • 2002
  • Since the high performance analog-to-digital converter can be built with Rapid Single Flux Quantum (RSFQ) logic circuits the development of superconductive analog-to-digital converter has attracted a lot of interests as one of the most prospective area of the application of Josephson Junction technology. One of the main advantages in using Rapid Sng1e Flux Quantum logic in the analog-to-digital converter is the low voltage output from the Josephson junction switching, and hence the high resolution. To design an analog-digital converter, first we have used XIC tool to compose a circuit schematic, and then studied the operational principle of the circuit with WRSPICE tool. Through this process, we obtained the proper circuit diagram of an 1-bit analog-digital converter circuit. The optimized circuit was laid out as a mask drawing. Inductance values of the circuit layout were calculated with L-meter.

Improved Constrained One-Bit Transform Using Adaptive Search Range (적응적 탐색 영역을 이용하여 개선한 제한된 1비트 변환 알고리즘)

  • Jang, Moon-Seok;Chung, Ki-Seok
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2013.11a
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    • pp.209-212
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    • 2013
  • 본 논문에서 적응적 탐색 영역(Adaptive Search Range)을 이용하여 개선한 제한된 1비트 변환 알고리즘을 제안하였다. 이 변환은 전역 검색 알고리즘 (Full Search Algorithm)을 사용한다. 그러나 이것은 매우 많은 연산량과 복잡도를 가진다. 제안된 알고리즘에서는 각 블록의 탐색범위를 결정하기 위한 움직임 벡터 (Motion Vector)와 함께 제한된 1비트 변환 알고리즘의 제한된 마스크 (Constrained Mask)를 사용한다. 실험결과를 통해 제안된 알고리즘은 움직임 예측의 정확도에 대한 성능을 비슷하게 유지하면서 평균적으로 Search Point의 수를 84% 줄일 수 있음을 보여준다.

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Design and Implementation of a RFID Transponder Chip using CMOS Process (CMOS 공정을 이용한 무선인식 송수신 집적회로의 설계 및 제작)

  • 신봉조;박근형
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.16 no.10
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    • pp.881-886
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    • 2003
  • This paper describes the design and implementation of a passive transponder chip for RFID applications. Passive transponders do not have their own power supply, and therefore all power required for the operation of a passive transponder must be drawn from the field of the reader. The designed transponder consists of a full wave rectifier to generate a dc supply voltage, a 128-bit mask ROM to store the information, and Manchester coding and load modulation circuits to be used for transmitting the information from the transponder to the reader. The transponder with a size 410 x 900 ${\mu}$m$^2$ has been fabricated using 0.65 ${\mu}$m 2-poly, 2-metal CMOS process. The measurement results show the data transmission rate of 3.9 kbps at RF frequency 125 kHz.