• Title/Summary/Keyword: bit data

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A Study on the Wear Condition Diagnosis of Grinding Wheel in Micro Drill-bit Grinding System (마이크로 드릴비트 연마 시스템 연삭휠의 마모 진단 연구)

  • Kim, Min-Seop;Hur, Jang-Wook
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.21 no.3
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    • pp.77-85
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    • 2022
  • In this study, to diagnose the grinding state of a micro drill bit, a sensor attachment location was selected through random vibration analysis of the grinding unit of the micro drill-bit grinding system. In addition, the vibration data generated during the drill bit grinding were collected from the grinding unit for the grinding wheels under the steady and worn conditions, and data feature extraction and dimension reduction were performed. The wear of the micro-drill-bit grinding wheel was diagnosed by applying KNN, a machine-learning algorithm. The classification model showed excellent performance, with an accuracy of 99.2%. The precision, recall and f1-score were higher than 99% in both the steady and wear conditions.

Improvement of Encoding Detection Algorithm for Multi-byte Encoded Data with Errors (오류가 발생한 멀티바이트 인코딩 데이터의 인코딩 기법 판별 알고리즘 개선)

  • Bae, Junwoo;Kim, Seonbeom;Park, Heejin
    • The Journal of Korean Institute of Next Generation Computing
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    • v.13 no.2
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    • pp.18-25
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    • 2017
  • In computer science, an encoding is a standardization of converting information to one format for audio, video or text. Therefore, the encoding information of the data should be known to open and read it and there are algorithms detecting encoder of the data. However, some informations of data could be disappeared by packet loss when transmitted on network, especially, if the data is snatched by packet sniffing or eavesdropping from wireless communications. In this paper, we improve the performance of encoding detection algorithm of 'uchardet' program for multi-byte encoded data with errors based on bit-shift algorithm. To simulate the performance, we generated Korean and Japanese text data with errors that is removed some random bits at random positions. Then the detection algorithm are tested using the data and 'uchardet-bitshift' showed better performance than 'uchardet'. When Korean texts are used, 'uchardet' could detect perfectly with ≤0.005% errors but it showed 0% detection rate with ≥1% errors while 'uchardet-bitshift' detected perfectly with ≤0.05% errors and it showed correct detection cases with ≥1% errors. Japanese texts with errors tend to report falsely as Chinese encoding because Japanese texts include lots of Chinese characters. As a results, we improved encoding detection algorithms by applying bit shift operation.

Design of ATM Adapter Circuit in the BSC for IMT-2000 Network (IMT-2000 망의 제어국에서 ATM 정합 회로 설계)

  • 이인환;이남준오돈성
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.55-58
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    • 1998
  • In this paper, we describe the design of the ATM adapter circuit in the BSC for IMT-2000 Network. This ATM adapter circuit can convert received ATM cell into TDM data in the BSC and vice versa. In the ATM adapter, we implemented both AAL1 and AAL5 functions to provide constant bit rate voice data and variable bit rate packet data servives, simultaneously.

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Probabilistic Bilinear Transformation Space-Based Joint Maximum A Posteriori Adaptation

  • Song, Hwa Jeon;Lee, Yunkeun;Kim, Hyung Soon
    • ETRI Journal
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    • v.34 no.5
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    • pp.783-786
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    • 2012
  • This letter proposes a more advanced joint maximum a posteriori (MAP) adaptation using a prior model based on a probabilistic scheme utilizing the bilinear transformation (BIT) concept. The proposed method not only has scalable parameters but is also based on a single prior distribution without the heuristic parameters of the previous joint BIT-MAP method. Experiment results, irrespective of the amount of adaptation data, show that the proposed method leads to a consistent improvement over the previous method.

The design of a 32-bit Microprocessor for a Sequence Control using an Application Specification Integrated Circuit(ASIC) (ICEIC'04)

  • Oh Yang
    • Proceedings of the IEEK Conference
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    • 2004.08c
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    • pp.486-490
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    • 2004
  • Programmable logic controller (PLC) is widely used in manufacturing system or process control. This paper presents the design of a 32-bit microprocessor for a sequence control using an Application Specification Integrated Circuit (ASIC). The 32-bit microprocessor was designed by a VHDL with top down method; the program memory was separated from the data memory for high speed execution of 274 specified sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. And in order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32-bits. And the real time debugging as single step run, break point run was implemented. Pulse instruction, step controller, master controllers, BIN and BCD type arithmetic instructions, barrel shit instructions were implemented for many used in PLC system. The designed microprocessor was synthesized by the S1L50000 series which contains 70,000 gates with 0.65um technology of SEIKO EPSON. Finally, the benchmark was performed to show that designed 32-bit microprocessor has better performance than Q4A PLC of Mitsubishi Corporation.

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A Buffer Management Scheme Using Prefetching and Caching for Variable Bit Rate Video-On-Demand Servers (가변 비트율 주문형 비디오 서버에서 선반입자 캐슁을 이용한 버퍼 관리 기법)

  • 김순철
    • Journal of Korea Society of Industrial Information Systems
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    • v.4 no.4
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    • pp.32-39
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    • 1999
  • Video-On-Demand servers have to provide timely processing guarantees and reduce the storage and reduce the storage and bandwidth requirements for continuous media However, compression techniques used in Video-On-Demand servers make the bit rates of compressed video data significantly variable from frame to frame Consequently, most pervious Video-On-Demand servers which use constant bit rate retrieval to guarantee deterministic service under-utilize the system resources and restrict the number of clients. In this paper, I propose a buffer management scheme called CAP(Caching And Prefetching) for Video-On-Demand server using variable bit rate continuous media. By caching and prefetching the data CAP reduces the variation of the compressed data and increases the number of clients simultaneously served and maximizes the utilization of system resources. Results of trace-driven simulations show the effectiveness of the scheme.

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Real-time 256-channel 12-bit 1ks/s Hardware for MCG Signal Acquisition (심자도 신호획득을 위한 실시간 256-채널 12-bit 1ks/s 하드웨어)

  • Yoo, Jae-Tack
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.54 no.11
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    • pp.643-649
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    • 2005
  • A heart diagnosis system adopts Superconducting Quantum Interface Device(SQUD) sensors for precise MCG(MagnetoCardioGram) signal acquisitions. Such system needs to deal with hundreds of sensors, requiring fast signal sampling md precise analog-to-digital conversions(ADC). Our development of hardware board, processing 64-channel 12-bit in 1 ks/s speed, is built by using 8-channel ADC chips, 8-bit microprocessors, SPI interfaces, and specially designed parallel data transfers between microprocessors to meet the 1ks/s, i.e. 1 mili-second sampling interval. We extend the design into 256-channel hardware and analyze the speed .using the measured data from the 64-channel hardware. Since our design exploits full parallel processing, Assembly level coding, and NOP(No Operation) instruction for timing control, the design provides expandability and lowest system timing margin. Our result concludes that the data collection with 256-channel analog input signals can be done in 201.5us time-interval which is much shorter than the required 1 mili-second period.

4-level Error Correcting Modulation Codes for Holographic Data Storage System (홀로그래픽 데이터 저장장치를 위한 4-레벨 오류정정 변조부호)

  • Lee, Jaehun;Lee, Jaejin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.39A no.10
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    • pp.610-612
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    • 2014
  • Mutilevel holographic data storage systems have a big advantage for capacity since it can store more than one bit per pixel. For instance, 2/3 modulation code stores 2/3(symbol/pixel) and 4/3(bit/pixel). Then it is about 1.3 bits per one pixel. In this paper, we propose two 4-level modulation codes, which have the minimum Euclidean distances of 3 and 4, respectively. The proposed codes perform better than random data. The performance of larger minimum distance code shows better than that of shorter one.

CDMA Digital Mobile Communications and Message Security

  • Rhee, Man-Young
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.6 no.4
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    • pp.3-38
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    • 1996
  • The mobile station shall convolutionally encode the data transmitted on the reverse traffic channel and the access channel prior to interleaving. Code symbols output from the convolutional encoder are repeated before being interleaved except the 9600 bps data rate. All the symbols are then interleaved, 64-ary orthogonal modulation, direct-sequence spreading, quadrature spreading, baseband filtering and QPSK transmission. The sync, paging, and forward traffic channel except the pilot channel in the forward CDMA channel are convolutionally encoded, block interleaved, spread with Walsh function at a fixed chip rate of 1.2288 Mcps to provide orthogonal channelization among all code channels. Following the spreading operation, the I and Q impulses are applied to respective baseband filters. After that, these impulses shall be transmitted by QPSK. Authentication in the CDMA system is the process for confirming the identity of the mobile station by exchanging information between a mobile station and the base station. The authentication scheme is to generate a 18-bit hash code from the 152-bit message length appended with 24-bit or 40-bit padding. Several techniques are proposed for the authentication data computation in this paper. To protect sensitive subscriber information, it shall be required enciphering ceratin fields of selected traffic channel signaling messages. The message encryption can be accomplished in two ways, i.e., external encryption and internal encryption.

A FPGA Implementation of a Rotary Machine Receiver with Detecting a Header on the Asynchronous Serial Communication System (비동기 방식의 직렬통신 시스템에서 헤드 검출 기능을 가진 회전기용 리시버의 FPGA 구현)

  • Kang, Bong-Soon;Lee, Chang-Hoon;Kim, In-Kyu;Ha, Ju-Young;Kim, Ju-Hyun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.1
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    • pp.88-94
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    • 2005
  • This paper presents the design and implementation of a receiver operating between a rotary machine encoder and DSP. The receiver connects with the encoder using 1 bit serial data and DSP using 16 bits bus line. The receiver and encoder use the different operating frequency each other. We suggest a new apparatus and method of synchronized code for header detection in 1bit serial communication. The system operating frequency can be changed into 20MHz or 60MHz by using the external port such as 'clk_select'.