• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.444-447
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• 2004

A heart diagnosis system adopts hundreds of Superconducting Quantum Interface Device(SQUID) sensors for precision MCG(Magnetocardiogram) or MEG(Magnetoencephalogram) signal acquisitions. This system requires correct and real-time data acquisition from the sensors in a required sampling interval, i.e., 1 mili-second. This paper presents our hardware design and test results, to acquire data from 256 channel analog signal with 1-ksample/sec speed, using 12-bit 8-channel ADC devices, SPI interfaces, parallel interfaces, and 8-bit microprocessors. We chose to implement parallel data transfer between microprocessors as an effective way of achieving such data collection. Our result concludes that the data collection can be done in 250 ${\mu}sec$ time-interval.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.418-425
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• 2012

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit pre-computation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weight-column code during the write operation and is designed by replacing 0's with 1's at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the odd-weight- column code, the implementation based on the proposed SEC-DED code with check bit pre-computation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.149-156
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• 2012

A digital input class-D audio amplifier is presented for digital hearing aid. The class-D audio amplifier is composed of digital and analog circuits. The analog circuit converts a digital input to a analog audio signal (DAC) with noise suppression in the audio band. An interpolated digital delta-sigma modulator is used to convert data types between digital signal processor (DSP) and digital-to-analog converter (DAC). An 16-bit, 25-kbps pulse code modulated (PCM) input is interpolated to 16-bit, 50-kbps by a digital filter. The output signal of interpolation filter is noise-shaped by a third-order digital sigma-delta modulator (SDM). As a result, 1.5-bit, 3.2-Mbps signal is applied to simple digital to analog converter.

• Journal of Digital Contents Society
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• v.17 no.3
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• pp.165-172
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• 2016

Morton codes play important roles in many parallel GPU applications for the nearest neighbor (NN) search in huge data and queries with its applications growing. This paper discusses and analyzes the meaning of Tero Karras's 32-bit 'unsigned int' Morton code algorithm for three-dimensional spatial information in $[0,1]^3$ and its geometric implications. Based on this, this paper proposes 64-bit 'unsigned long long' version of Morton code and compares the results in both CPU vs. GPU and 32-bit vs. 64-bit versions. The proposed GPU algorithm runs around 1000 times faster than the CPU version.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.252-255
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• 2004

This paper presents a new technique to generate the 1-bit signal by decoding Pulse Width Modulation (PWM) signal to a binary file before programming onto the ROM. Since each PWM signal requires only 1-bit digital signal, PWM signal and other forms of digital signal related to multi-bit can be simply generated. The results demonstrate that using this new technique to generate the PWM signal can simplify the process and hardware complication. Moreover, the signal's data and frequency can be easily modified by programming the data onto the ROM and using the counter, respectively, which can reduce the size of the circuit and make the PCB easier.

• Journal of the Optical Society of Korea
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• v.20 no.4
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• pp.464-469
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• 2016

All-optical non-return-to-zero (NRZ) -to- return-to-zero (RZ) data-format conversion has been successfully demonstrated using a semiconductor optical amplifier in a fiber-loop mirror (so-called SOA-loop mirror) with a continuous-wave (CW) holding beam. The converted RZ signal after pulse compression has been used to create a 40 Gb/s OTDM (Optical Time Division Multiplexing) signal. Here is proposed an NRZ-to-RZ conversion method without any additional optical clocks, unlike conventional methods based on optical AND logic. In addition, it has the merit of operating at various bit-rate speeds without any controlling device. Moreover, it has a simple structure, and it can be used for all-optical bit-rate-flexible clock recovery.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.7
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• pp.1716-1725
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• 1996

In this paper, the huffman decoder which is a part of the decoder in JPEG standard format is designed by using a new Ternary CAM. First, the 256 word * 16 bit-size new bit-word all parallel Ternary CAM system is designed and verified using SPICE and CADENCE Verilog-XL, and then the verified novel Ternary CAM is applied to the new huffman decoder architecture of JPEG. So the performnce of the designed CAM cell and it's block is verified. The new Ternary CAM has various applications because it has search data mask and storing data mask function, which enable bit-wise search and don't care state storing. When the CAM is used for huffman look-up table in huffman decoder, the CAM is partitioned according to the decoding symbol frequency. The scheme of partitioning CAM for huffman table overcomes the drawbacks of all-parallel CAM with much power and load. So operation speed and power consumption are improved.

• Genomics & Informatics
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• v.20 no.3
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• pp.36.1-36.6
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• 2022

BLAST, a basic bioinformatics tool for searching local sequence similarity, has been one of the most widely used bioinformatics programs since its introduction in 1990. Users generally use the web-based NCBI-BLAST program for BLAST analysis. However, users with large sequence data are often faced with a problem of upload size limitation while using the web-based BLAST program. This proves inconvenient as scientists often want to run BLAST on their own data, such as transcriptome or whole genome sequences. To overcome this issue, we developed NBLAST, a graphical user interface-based BLAST program that employs a two-way system, allowing the use of input sequences either as "query" or "target" in the BLAST analysis. NBLAST is also equipped with a dot plot viewer, thus allowing researchers to create custom database for BLAST and run a dot plot similarity analysis within a single program. It is available to access to the NBLAST with http://nbitglobal.com/nblast.

• Journal of IKEEE
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• v.16 no.3
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• pp.265-273
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• 2012

Data stability and leakage power dissipation have become a critical issue in scaled SRAM design. In this paper, an advanced 8T SRAM cell improving the read and write stability of data storage elements as well as reducing the leakage current in the idle mode is presented. During the read operation, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level, and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In the write operation, a negative bias on the cell facilitates to change the contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In the standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates almost 100 % higher read stability while bearing 20 % better write-ability at 1.2 V typical condition, and a reduction by 45 % in leakage power consumption compared to the standard 6T cell. The stability enhancement and leakage power reduction provided with the proposed bit-cell are confirmed under process, voltage and temperature variations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.9
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• pp.1667-1671
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• 2015

Multi-level holographic data storage is a candidate for the next generation data storage system, since it can store more than one bit per pixel. It is possible to increase the number of codewords if the number of levels is increased, and the code with an appropriate selection of codewords can also increase the minimum distance. In this paper, we propose three multi-level modulation codes of the code rate 1 bit/pixel and compare the performance according to the minimum distance. The result shows that the code with small number of levels is better than that of large number of levels because it is hard to detect threshold value.