• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.339-344
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• 2014

This paper presents a novel bipolar junction transistor (BJT) based electrostatic discharge (ESD) protection device. This protection device was designed for 20V power clamps and fabricated by a process with Bipolar-CMOS-DMOS (BCD) $0.18{\mu}m$. The current-voltage characteristics of this protection device was verified by the transmission line pulse (TLP) system and the DC BV characteristic was verified by using a semiconductor parameter analyzer. From the experimental results, the proposed device has a trigger voltage of 29.1V, holding voltage of 22.4V and low on-resistance of approximately $1.6{\Omega}$. In addition, the test of ESD robustness showed that the ESD successfully passed through human body model (HBM) 8kV. In this paper, the operational mechanism of this protection device was investigated by structural analysis of the proposed device. In addition, the proposed device were obtained as stack structures and verified.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.1
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• pp.7-12
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• 1984

In this paper, the authors applied the method of hydrogen chloride gettering oxidation to fabricate the low noise bipolar transistor. The results of measurements of the effect of guttering on the variation of flicker noise spectral intensity for variable HCI concentrations indicate that flicker noise in bipolar than-sistor is dependent on the surface condition and that the gettering in a mixture of 2% HCI in oxidation produced the optimal results in the fabrication of the low noise device. In addition, it was also noted that the PSG layer formed by the emitter source (phosphorus) did not have so much guttering effect as in the process with HCl getterinng.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1901-1911
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• 2018

This study presents a circuit model for simulating the switching transients of insulated-gate bipolar transistors (IGBTs) with inductive load switching. The modeling approach used in this study considers the behavior of IGBTs and freewheeling diodes during the transient process and ignores the complex semiconductor physics-based relationships and parameters. The proposed circuit model can accurately simulate the switching behavior due to the detailed consideration of device-circuit interactions and the nonlinear nature of model parameters, such as internal capacitances. The developed model is incorporated in an IGBT loss calculation module of an electromagnetic transient simulation program to enable the estimation of switching losses in voltage source converters embedded in large power systems.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.52-52
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• 2009

In this work, we demonstrate the modelling and simulation of the AlGaAs/GaAs quantum-well based light emitting transistor(LET). Based on the experimental and theoretical model, we have compared between a heterojunction bipolar transistor(HBT) structure with quantum wells in the base region and a HBT without quantum wells in the base region. For the purpose of optimizing device design, several analytic and numerical studies have been presented.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.7
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• pp.1363-1374
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• 2009

This paper reviews the characteristics and technical trends in Power MOSFET technology that are leading to improvements in power loss for power electronic system. The silicon bipolar power transistor has been displaced by silicon power MOSFET's in low and high voltage system. The power electronic technology requires the marriage of power device technology with MOS-gated device and bipolar analog circuits. The technology challenges involved in combining power handling capability with finger gate, trench array, super junction structure, and SiC transistor are described, together with examples of solutions for telecommunications, motor control, and switch mode power supplies.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.510-510
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• 2000

This paper introduces the design of BiCMOS latched comparator circuit for high-speed system application, which can be used in data conversion, instrumentation, communication system etc. By exploiting the advantage technology of the combination of both the bipolar transistor and the CMOS transistor devices. The comparator circuit includes an input stage that combines MOS sampling with a bipolar regenerative amplifier. The resistive load of conventional current-steering comparator is replaced by a load, which is made by a NMOS transistor. The advantage of design and PSPICE simulation of BiCMOS latched comparator are the circuit will obtain wide bandwidth with lowest power consumption at a single supply voltage. All the characteristics of the proposed BiCMOS latched comparator circuit is carried out by simulation program.

• Proceedings of the KSR Conference
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• 2009.05a
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• pp.1943-1950
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• 2009

The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO (Gate Turnoff Thyristor) technology. The IGBT combines the advantages of a power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) and a bipolar power transistor. The change of electrical characteristics for IGBT is mainly coming from the change of characteristics of MOSFET at the input gate and the PNP transistors at the output. The gate oxide structure gives the main influence on the changes in the electrical characteristics affected by environments such as radiation and temperature, etc.. The change of threshold voltage, which is one of the important design parameters, is brought by charge trapping at the gate oxide. In this paper, the electrical characteristics are simulated by SPICE simulation, and the parameters are found to design optimized circuits.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.10
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• pp.20-26
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• 1993

The base-collector capacitance of an npn bipolar transistor in bipolar or BiCMOS technology has significant influence on the switching performances, and comprises pnjunction component and MOS component. Both components have complicated dependences on the isolation oxide structure, epitaxial doping density, and bias voltage. Analytical/empirical formulas for both components are derived in this paper for a generic isolation structure as a function of epitaxial doping density and bias voltage based on some theoretical understanding and two-dimensional device simulations. These formulas are useful in estimating the effect of device isoation schemes on the switching speed of bipolar transistors.

• KIPE Magazine
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• v.22 no.1
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• pp.42-50
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• 2017

• Electrical & Electronic Materials
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• v.9 no.10
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• pp.1066-1073
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• 1996