• Journal of the Korean Institute of Telematics and Electronics
• /
• v.19 no.5
• /
• pp.20-25
• /
• 1982

A realization method of the microwave oscillator is proposed by the inherently stable transistor with a cavily resonator feedback loop. The real Part of the output impedance of the inherently stable bipolar transistor can be made to be negative at the resonance frequency by the high-Q cavity feedback loop, and the oscillation condition can be obtained with the matching section of the load. In this work the microwave transistor oscillator is realized with a silicon bipolar transistor HXTR 2101 and a reentrani cavity, and characteristic of the output power 10m Watts at 2.33 GHz osc. frequency can be verified experimentally.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 1999.05a
• /
• pp.415-419
• /
• 1999

Many bipolar logic circuit of conventional occurred problem of speed delay according to deep saturation state of vertical NPN Transistor. In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. The structure of Gate consists of the vertical NPN Transistor, substrate and Merged PNP Transistor. In the result, we fount that tarriers which are coming into intrinsic Base from Emitter and the portion of edge are relatively a lot, so those make Base currents a lot and Gain is low with a few of collector currents because of cutting the buried layer of collector of conventional junction area. Merged PNP Transistor's currents are low because Base width is wide and the difference of Emitter's density and Base's density is small. we get amplitude of logic voltage of 200mv, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26nS in AC characteristic output of Ring-Oscillator connected Gate.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.24 no.5
• /
• pp.786-793
• /
• 1987

This paper describes the design and fabrication of the polysilicon selfaligned bipolar transistor with 1.6\ulcorner epitaxy and SWAMI isolation technologies. This transistor has two levels of polysilicon. Also emitter and adjacent edge of polysilicon base contact of this PSA device are defined by the same mask, and emitter feature size is 2x4 \ulcorner. DC characteristic of the fabricated transistor was evaluated and analyzed for the SPICE input parameters. The minimum propagation delay time per gate of 330 ps at 1mW was obtained with 41 stage CML ring oscillator.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.23 no.6
• /
• pp.741-746
• /
• 1986

A novel n-p-n bipolar transistor of which emitter is self-aligned with base contact by polyilicon is developed for using in high speed and high packing density LSI circuits. The emitter of this transistor is separated less than 0.4 \ulcorner with base contact by self-aligh technology, and the emitter feature size is less than 3x5 \ulcorner\ulcorner Because the active region of this transistor is not damaged through all the process, it has excellent electric properties. Using the n-p-n transistors by 3.0\ulcorner design rules, a NTL ring oscillator has 380 ps, a CML ring oscillator has 390ps, and a I\ulcorner ring oscillator has 5.6ns of per-gate minimum propagation delay time.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.10
• /
• pp.25-34
• /
• 1995

A new vertical power MOSFET with over-current protection capability is proposed. The MOSFET consists of main power MOSFET cell, sensing MOSFET cell and lateral npn bipolar transistor. The proposed MOSFET may be fabricated by a conventional DMOS process without any additional fabrication step. Overcurrent state is sensed by the newly designed lateral bipolar transistor. Mixed-mode simulations proved that the overcurrent protection is achieved by the proposed MOSFET successfully with a small protection area less than 0.2 % of the total die area.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.49-52
• /
• 2002

A new method is developed to extract model parameters of SiGe HBT equivalent circuit including the base impedance and base-collector junction capacitance. Using this method, all resistances and capacitances of SiGe HBT are independently determined from measured S-parameters using two-port parameter formula. This method is proposed to reduce possible errors generated from global optimization process, and its accuracy has been verified by finding good agreements between measured and modeled current / power gain up to 18 GHz.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.3
• /
• pp.88-94
• /
• 1993

In this paper, a simple Ebers-Moll Model for the heterojunction bipolar transistor is presented. Using the model structure for the npn type HBT, the current-voltage characteristics was analyzed. And from the obtained terminal currents, the Ebers-Moll equations were derived. Then substituting the physical parameters for heterojunction to those for homojunction, this model would be used to analyze the characteristics of single and/or duble heterojunction HBT's. And directly relating model parameters to device parameters, it would be also used to optimize the characteristics of HBT's. The simulated results using this model were in good agreement with experimental data.

• The Magazine of the IEIE
• /
• v.14 no.1
• /
• pp.64-69
• /
• 1987

• Korean Journal of Air-Conditioning and Refrigeration Engineering
• /
• v.30 no.1
• /
• pp.1-9
• /
• 2018

Thermal performance of a heat sink for an inverter power stack was analyzed in terms of array and installation location of an Insulated Gate Bipolar Transistor (IGBT). Thermal flow around the heat sink was calculated with a numerical model that could simulate forced convection. Thermal performance was calculated depending on the array and location of high- and low-power IGBTs considering the maximum temperature of IGBT. The optimum array and installation location were found and causes were analyzed based on results of numerical analysis. For the numerical analysis, experiment design considered the installation location of IGBT, ratio of heat generation rates of high- and low-power IGBTs, and velocity of the inlet air as design variables. Based on numerical results, a correlation that could calculate thermal performance of the heat sink was suggested and the maximum temperature of the IGBT could be predicted depending on the installation method.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.359-359
• /
• 2010

IGBT(Insulated Gate Bipolar Transistor) 란 MOS(Metal Oxide Silicon) 와 Bipolar 기술의 결정체로 낮은 순방향 손실(Low Saturation)과 빠른 Speed를 특징으로 기존의 Thyristor, BJT, MOSFET 등으로 실현 불가능한 분양의 응용처를 대상으로 적용이 확대 되고 있고, 300V 이상의 High Power Application 영역에서 널리 사용되고 있는 고효율, 고속의 전력 시스템에 있어서 필수적으로 이용되는 Power Device이다. IGBT는 출력 특성 면에서 Bipolar Transistor 이상의 전류 능력을 가지고 있고 입력 특성 면에서 MOSFET과 같이 Gate 구동 특성을 갖기 때문에 High Switching, High Power에 적용이 가능한 소자이다. 반면에, Conventional IGBT는 MOSFET과 달리 IGBT 내부에 Anti-Parallel Diode가 없기 때문에 Inductive Load Application 적용시에는 별도의 Free Wheeling Diode가 필요하다. 그래서, 본 논문에서 별도의 Anti-Parallel Diode의 추가 없이도 Inductive Load Application에 적용 가능한 RC IGBT를 적용하여 600V/15A급 Three Phase Inverter Module을 제안 하고자 한다.