• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.183-186
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• 1999

The Ultra-miniature and low phase noise Colpitts VCO of 0.06㏄ in size has been developed using the high Q resonator and phase compensation technique. This type is one transistor VCO without a buffer. To design and simulate the VCO accurately, nolinear model parameters of a bipolar transistor are extracted using the measured I-V data and S parameters based on the Gummel-Poon model. Design and simulation have been done by Serenade 7.5 design tool using the extracted nonlinear model parameters. The wideband VCO has been designed using two varactor diodes and open loop gain compensation technique to improve the operating frequency range. The ultra-miniature VCO has shown the phase noise of -91㏈c/Hz at 10KHz offset and output power of -3㏈m The wideband VCO has shown the tuning frequency bandwidth of 150MHz phase noise of -95㏈c/Hz at 10KHz offset and output power of 5㏈m.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.274-280
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• 2007

This paper demonstrates an efficiency improvement of the class E power amplifier (PA) by tuning-out the input capacitance ($C_{IN}$) of the power HBT with a shunt inductance. In order to obtain high output power, the PA needs the large emitter size of a transistor. The larger the emitter size, the higher the parasitic capacitance. The parasitic $C_{IN}$ affects the distortion of the voltage signal at the base node and changes the duty cycle to decrease the PA's efficiency. Adopting the L-C resonance, we obtain a remarkable efficiency improvement of as much as 7%. This PA exhibits output power of 29 dBm and collector efficiency of 71% at 1.9 GHz.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 추계학술대회 논문집 학회본부
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• pp.692-696
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• 1997

본 연구에서는 BJT(Bipolar Junction Transistor)와 MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 등을 1MeV에너지의 전자빔을 선량을 변화시켜가며 조사시켜 그 특성 변화를 분석하였다. BJT에 대해서는 조사 전, 후의 전류 이득의 측정을 통해 base 에서의 minority-carrie의 수명 변화에 의해서 전류 이득이 감소하는 것으로 나타났으며, MOSFET의 경우는 oxide 지역의 전하량 변화에 의해서 문턱 전압이 영향을 받음을 확인할 수 있었다. BJT의 minority-carrier의 수명 감소량은 조사 선량이 증가함에 따라 직선적으로 변화함을 알 수 있었고, MOSFET의 문턱 전압의 변화는 nMOS와 pMOS의 경우 서로 다름을 관찰할 수 있었는데 이는 oxide내에서 발생하는 전하에 의해 차이가 남을 알 수 있었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 추계학술대회 논문집 전기물성,응용부문
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• pp.97-98
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• 2006

High current behaviors of extended drain n-type metal-oxide-semiconductor field effects transistor (EDNMOS) with double polarity source (DPS) for electrostatic discharge (ESD) protection are analyzed. Simulation based contour analyses reveal that combination of bipolar junction transistor operation and deep electron channeling induced by high electron injection gives rise to the second on-state. Therefore, the deep electron channel formation needs to be prevented in order to realize stable and robust ESD protection performance. Based on our analyses, general methodology to avoid the double snapback and to realize stable ESD protection is to be discussed.

• ETRI Journal
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• 제27권4호
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• pp.449-452
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• 2005

The electrical characteristics of solid state devices such as the bipolar junction transistor (BJT), metal-oxide semiconductor field-effect transistor (MOSFET), and other active devices are altered by impinging photon radiation and temperature in the space environment. In this paper, the threshold voltage, the breakdown voltage, and the on-resistance for two kinds of MOSFETs (200 V and 100 V of $V_{DSS}$) are tested for ${\gamma}-irradiation$ and compared with the electrical specifications under the pre- and post-irradiation low dose rates of 4.97 and 9.55 rad/s as well as at a maximum total dose of 30 krad. In our experiment, the ${\gamma}-radiation$ facility using a low dose, available at Korea Atomic Energy Research Institute (KAERI), has been applied on two commercially available International Rectifier (IR) products, IRFP250 and IRF540.

• 한국통신학회논문지
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• 제10권3호
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• pp.105-114
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• 1985

無條件 安定인 超高周波用 바이폴라 트랜지스터를 使用하여 S 밴드에서의 發振器를 具現하여 보았다. 發振器는 周波數安定한 3個의 同一한 誘電體 共振器를 利用하여 製作되었으며 負性 抵抗은 3포트 散亂係數(3-Ports Scattering Parameters) 方法으로 求하였다. 本 論文에서는 誘電體 共振器를 궤환素子로 使用하여 콜렉터, 베이스에서 各各 41dBm, 10dmB의 最大出力을 얻을 수 있었다.

• 대한전기학회논문지
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• 제45권2호
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• pp.230-234
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• 1996

A new trenched Hybrid Schottky INjection Field Effect Transistor (HSINFET) is proposed and verified by 2-D semiconductor device simulation. The feature of the proposed structure is that the hybrid Schottky injector is implemented at the trench sidewall and p-n junction injector at the upper sidewall and bottom of a trench. Two-dimensional simulation has been performed to compare the new HSINFET with the SINFET, conventional HSINFET and lateral insulated gate bipolar transistor(LIGBT). The numerical results shows that the current handling capability of the proposed HSINFET is significantly increased without sacrificing turn-off characteristics. The proposed HSINFET exhibits higher latch-up current density and much faster switching speed than the lateral IGBT. The forward voltage drop of the proposed HSINFET is 0.4 V lower than that of the conventional HSINFET and the turn-off time of the trenched HSINFET is much smaller than that of LIGBT.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전기물성,응용부문
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• pp.141-144
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• 2002

The method of the analysis of the base Gummel number of the PNP BJT(Bipolar Junction Transistor) for integrated circuits based upon the semiconductor physics is proposed and the method of calculating the doping profile of the base region using process conditions is presented. The transistor saturation current obtained from the proposed method of PNP BJT using 20V and 30V process shows an averaged relative error of 6.7% compared with the measured data.

• ETRI Journal
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• 제9권1호
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• pp.118-124
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• 1987

Short channel n-MOSFET의 드레인-소오스 사이의 breakdown은 단순한 접합 breakdown이 아닌 avalanche-induced breakdown으로 p-MOSFET, long channel n-MOSFET의 breakdown 전압보다 훨씬 작은 값을 갖는다. Short channel n-MOSFET의 breakdown의 특징은 current-controlled 부저항 특성(snapback)이 나타나고, 게이트 전압에 따라 breakdown 전압보다 작은 sustainning 전압이 존재한다. 이와 같은 sustainning 전압은 short channel n-MOSFET의 안정한 동작에 또 하나의 제한 요소가 될 수 있다. 따라서 공정 및 회로 시뮬레이션을 위해, short channel n-MOSFET의 avalanche breakdown 현상에 대한 정확한 분석이 요구된다. Short channel n -MOSFET의 avalanche breakdown 현상을 분석하기 위해서Parasitic bipolar transistor를 도입한 분석적 모델을 이용하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
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• pp.357-360
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• 2000

This paper describes a parameter extraction method for HBT(Heterojunction Bipolar Transistor) equivalent circuit model without measurements of special test structures or numerical optimizations. Instead, all equivalent circuit parameters are calculated analytically from small-signal S-parameters measured under different bias conditions. These values being extracted from the cutoff mode can be used to extract intrinsic parameters at the active mode. This method yields a deviation of about 1.3 % between the measured and modeled S-parameters.