• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.103-108
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• 2006

This paper proposed a low power resource allocation algorithm for the minimum switching activity of operators in high level synthesis. In this paper, the proposed method finds switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To use the switching activity was found the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step. As the existing method, the execution time can be fast according to use the number of operator and maximal control step. And it is the reduction effect from 8.5% to 9.3%.

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.134-140
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• 2006

This paper proposed a low power resource allocation algorithm for the minimum switching activity of operators in high level synthesis. In this paper, the proposed method finds switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To use the switching activity was found the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step. As the existing method, the execution time can be fast according to use the number of operator and maximal control step. And it is the reduction effect from 8.5% to 9.3%.

• Proceedings of the KIEE Conference
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• 2003.04a
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• pp.303-305
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• 2003

This paper discusses single-phase AC-DC converter that driven by binary combination at different transformer winding ratio. It has a advantage that constructs a control system simply and obtain load current of good quality without filter circuit and free from noise or isolation for lower switching frequency. Also, this has merit that can do high power capacity. In this research, study on feedback circuit that consist for load stability of AC-DC multi-level converter.

• Proceedings of the KIEE Conference
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• 2007.04c
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• pp.180-182
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• 2007

An interior permanent magnet synchronous motors (IPMSM) are receiving increased attention for many industrial applications because of its high torque to inertia ratio, superior power density, and high efficiency. This paper presents algorithm for speed sensorless control based on an adaptive binary observer adding the fuzzy gain compensator. Effectiveness of algorithm is confirmed by the experiments.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.2
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• pp.1-8
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• 1990

The unequal bit-error control of rate r=b/n binary convolutional code is analyzed. The error protection afforded to each digit of the viterbi decoded b-tuple information word can be different from that afforded to other digit. The property of the unequal protection can be applied for improvement of SNR in transmitting sampled data of DPCM system.

• Journal of the Korea Society for Simulation
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• v.17 no.1
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• pp.17-22
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• 2008

Double-binary turbo code has been adopted as an error control code of various future communication systems including wireless metropolitan area networks(WMAN) due to its powerful error correction capability. One of the components affecting the performance of turbo code is internal interleaver. In 802.16 d/e system, an almost regular permutation(ARP) interleaver has been included as a part of specification, however it seems that the interleaver is not optimized in terms of decoding performance. In this paper, we propose three optimization methods for the interleaver based on spatial distance, spread and minimum distance between original and interleaved sequence. We find optimized interleaving parameters for each optimization method and evaluate the performances of the proposed methods by computer simulation under additive white Gaussian noise(AWGN) channel. Optimized parameters can provide up to 1.0 dB power gain over the conventional method and furthermore the obtainable gain does not require any additional hardware complexity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.9
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• pp.2131-2139
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• 2014

In this paper, a binary-coded physical-layer network coding (PNC) is considered when high-order modulation techniques are used at source nodes in wireless communication environments. In the conventional PNC schemes, tight power control and phase compensation are required at a relay node. However, they may not be feasible in practical wireless communication environments. Thus, we do not assume the pre-equalization in this paper, and we only utilize the channel state information at receiver (CSIR). We propose a signal detection method for the binary-coded PNC with high-order modulation, such as QPSK and 16QAM, at the source nodes, while the conventional scheme only consider the BPSK at source nodes. We also analyze the bit-error performance of the proposed technique in both uncoded and coded cases.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.11
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• pp.12-19
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• 2015

In network-centric warfare, the communication network has played a significant role in defeating an enemy. Especially, the urgent and important data should be preferentially delivered in time. Thus, we proposed a priority MAC protocol based on CSMA/CA with Binary Exponential Back-off for tactical wireless networks. This MAC protocol suggested a PCW(Prioritized Contention Window) with differentiated back-off time by priority and a RBR(Repetitive Back-off Reset) to reset the remaining back-off time. The results showed that this proposed MAC has higher performance than those of DCF(Distributed Coordination Function) in the transmission success rate and the number of control packet transmission by reducing the packet collision. Thus, it produced more effective power consumption. In comparison with DCF, this proposed protocol is more suitable in high-traffic network.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.5
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• pp.1143-1150
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• 2000

A dual-mode multiplier (DMM) that performs single- and double-precision multiplications has been designed using a $0.25-\mum$ 5-metal CMOS technology. An algorithm for efficiently implementing double-precision multiplication with a single-precision multiplier was proposed, which is based on partitioning double-precision multiplication into four single-precision sub-multiplications and computing them with sequential accumulations. When compared with conventional double-precision multipliers, our approach reduces the hardware complexity by about one third resulting in small silicon area and low-power dissipation at the expense of increased latency and throughput cycles. The DMM consists of a $28-b\times28-b$ single-precision multiplier designed using radix-4 Booth receding and redundant binary (RB) arithmetic, an accumulator and a simple control logic for mode selection. It contains about 25,000 transistors on the area of about $0.77\times0.40-m^2$. The HSPICE simulation results show that the DMM core can safely operate with 200-MHZ clock at 2.5-V, and its estimated power dissipation is about 130-㎽ at double-precision mode.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.3
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• pp.449-458
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• 2022

In a power plant, the utility operates controllers include safety program that has performed several stages verification to prevent accidents in preparation for accidents, or to stably operate in accident. This paper describes the virtualization technology so that the verified binary operating system and application program can operate on the controller processor used in the power plant safety control facility. The technology applied to this virtualization processor uses commercial tools to implement the essential components for the operation of the safety-grade controller processor module, such as command interpreters and analyzers, and the virtualization platform was developed in a Linux-based operating system using the Imperas Tool. In addition, it was checked whether the implemented virtual processor module can normally interpret and execute binary-type instructions.