• Journal of Broadcast Engineering
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• 제22권5호
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• pp.541-547
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• 2017

The Joint Exploration Model (JEM), which is a reference SW codec of the Joint Video Exploration Team (JVET) exploring the future video standard technology, provides a recursive Quadtree plus Binary Tree (QTBT) block structure. QTBT can achieve enhanced coding efficiency by adding new block structures at the expense of largely increased computational complexity. In this paper, we propose a fast decision algorithm of QTBT block partitioning depth that uses the rate-distortion (RD) cost of the upper and current depth to reduce the complexity of the JEM encoder. Experimental results showed that the computational complexity of JEM 5.0 can be reduced up to 21.6% and 11.0% with BD-rate increase of 0.7% and 1.2% in AI (All Intra) and RA (Random Access), respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• 제46권7호
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• pp.39-44
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• 2009

It is well-known that the performance of turbo codes can be improved by allocating different energies per code symbol. In this paper, based on this observation, we propose a joint encoding and modulation scheme for quadrature amplitude modulated turbo code systems. In the proposed scheme, the amount of energy difference between the turbo coded symbols is optimized by optimizing the constellation of quadrature amplitude modulation (QAM). The proposed scheme offers better coding gain compared to the conventional combination of binary turbo code and QAM at the bit error rate of 10$^{-5}$. Also, the performance of binary turbo codes with the proposed QAM constellation for various code symbol mapping strategies are verified.

• Journal of IKEEE
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• 제10권2호통권19호
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• pp.128-133
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• 2006

This paper describes a high speed interface circuit using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that converts redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, the proposed 1:4 DEMUX (demultiplexer, serial-parallel converter), was designed using a 0.35um standard CMOS technology. Proposed DEMUX is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW. The operating speed of this circuit is limited by the maximum frequency which the 0.35um process has. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 10Gb/s in submicron process of high operating frequency.

• Journal of Advanced Navigation Technology
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• 제18권6호
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• pp.600-608
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• 2014

In this paper, CABAC H/W module is developed using co-design method. After entire H.264/AVC encoder was developed with C using reference SW(JM), CABAC H/W IP is developed as a block in H.264/AVC encoder. Context modeller of CABAC is included on the hardware to update the changed value during binary encoding, which enables the efficient usage of memory and the efficient design of I/O stream. Hardware IP is co-operated with the reference software JM of H.264/AVC, and executed on Virtex-4 FX60 FPGA on ML410 board. Functional simulation is done using Modelsim. Compared with existing H/W module of CABAC with register-level design, the development time is reduced greatly and software engineer can design H/W module more easily. As a result, the used amount of slice in CABAC is less than 1/3 of that of CAVLC module. The proposed co-design method is useful to provide hardware accelerator in need of speed-up of high efficient video encoder in embedded system.

• Journal of the Korean Institute of Telematics and Electronics S
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• 제35S권10호
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• pp.11-18
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• 1998

A binary line code, called MB46d, is designed by use of the BUDA(Binary Unit DSV and ASV) cell concept to retain the property of being runlength limited, DC tree, and with a power spectral null at the Nyquist frequency. This new code is a stateless line code with a simple encoding and a decoding rule and enables efficient error monitoring. The power spectrum and the eye pattern of the new line code are simulated for a minimum-bandwidth digital transmission system where the sinc function is used as a basic pulse. The obtained power null at the Nyquist frequency is wide enough to enable easy band-limiting as well as secure insertion of a clock pilot where necessary. The eye is also substantially wide to tolerate a fair amount of timing jitter in the receiver.

• Journal of Plant Biotechnology
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• 제6권1호
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• pp.21-24
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• 2004

A modified $\delta$-endotoxin gene of Bacillus thuringiensis ssp. tenebrionis (B.t.t.), encoding a coleoptera-specific toxin, was utilized to transform citrus plants, Citrus reticulata Blanco 'Ponkan' mandarian. By co-culturing the nucelli with Agrobacterium tumefaciens harboring the modified gene in the binary vector pBinAR-Btt, the chimeric toxin gene was transferred into citrus plants. The transgenic plants were selected on modified Murashige and Skoog medium containing kanamycin. Hybridization experiments demonstrated that the transgenic plants contained and expressed the toxin protein gene.

• Journal of IKEEE
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• 제13권1호
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• pp.65-70
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• 2009

We propose an ultrashort pulse optical code-division multiple-access (O-CDMA) scheme based on a pseudorandom binary M-sequence spectral phase encoding and decoding of coherent mode-locked laser pulses and perform a numerical simulation to analyze its feasibility. We demonstrate the ability to properly decode any of the multiple (eight) 10 Gbit/s users by the matched code selection of the spectral phase decoder. The peak power signal to noise ratio of properly and improperly decoded $8{\times}10 Gb/s$ signals could be greater than 15 for 127 M-sequence coding.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.699-702
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• 2005

This paper describes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit and decoding circuit. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 DEMUX (demultiplexer) was designed using a 0.35um standard CMOS technology. Proposed circuit is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW.

• Journal of the Optical Society of Korea
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• 제14권2호
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• pp.97-103
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• 2010

We propose a new technique for the optical encryption of gray-level optical images digitized into 8-bits binary data by ASCII encoding followed by QPSK modulation. We made an encrypted digital hologram with a security key by using 2-step phase-shifting digital holography, and the encrypted digital hologram is recorded on a CCD camera with 256 gray-level quantized intensities. With these encrypted digital holograms, the phase values are reconstructed by the same security key and are decrypted into the original gray-level optical image by demodulation and decoding. Simulation results show that the proposed method can be used for cryptosystems and security systems.

• Journal of Electrical Engineering and Technology
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• 제3권3호
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• pp.430-435
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• 2008

In the paper, an algorithm called a Constraint algorithm is proposed to solve the fan-in problem occurred in ADC encoding circuits. The Flash ADC architecture uses a double-base number system (DBNS). The DBNS has known to represent the multi-dimensional logarithmic number system (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in digital signal processing (DSP) applications. The authors use the DBNS with the base 2 and 3 to represent binary output of ADC. A symmetric map is analyzed first, and then asymmetric map is followed to provide addition read DBNS to DSP circuitry. The simulation results are shown for the Double-Base Integer Encoder (DBIE) of the 6-bit ADC to demonstrate an effectiveness of the Constraint algorithm, using $0.18{\mu}\;m$ CMOS technology. The DBIE’s processing speed of the ADC is fast compared to the FAT tree encoder circuit by 0.95 GHz.