• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2017.06a
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• pp.254-255
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• 2017

HEVC(High Efficiency Video Coding) 보다 뛰어난 압축 성능을 갖는 차세대 비디오 부호화 표준 기술 탐색을 하고 있는 JVET(Joint Video Exploratory Team)에서는 기술 검증을 위한 참조 SW 코덱인 JEM(Joint Exploration Model)을 공개하고 있다. JEM 의 화면내 예측 부호화에서는 67 가지의 예측모드를 사용하고 6 개의 MPM(Most Probable Mode)을 이용하여 예측모드를 부호화 한다. 본 논문에서는 코딩블록에서의 화면내 예측모드의 선택 확률을 바탕으로 보다 효율적인 예측모드 부호화 기법을 제안한다. 실험결과 JEM 5.0 대비 MPM 을 포함한 예측모드 부호화 정보의 CABAC(Context Adaptive Binary Arithmetic Coding) 엔트로피 부호화를 제외하고, AI(All Intra) 부호화 구조에서 0.23% 정도의 BD-rate 감소를 보임을 확일 할 수 있었다.

• Journal of Broadcast Engineering
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• v.23 no.4
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• pp.495-502
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• 2018

JVET (Joint Video Exploration Team) which explored evolving technologies of video coding with capabilities beyond HEVC (High Efficiency Video Coding), released a references software codec named the Joint Exploration Model (JEM) for performance verification of coding technologies. JEM has 67 intra prediction modes that extend the 35 modes of HEVC for intra prediction. Therefore, the enhancement of the coding performance is limited due to the overhead of prediction mode coding. In this paper, we analyze the probabilities of prediction modes selections, and then we propose a more efficient intra prediction mode coding based on the results of analyzed mode occurrence. In addition, we propose a context modeling for CABAC (Context-Adaptive Binary Arithmetic Coding) of the proposed mode coding. Experimental results show that the BD-rate gain is 0.02% on the AI (All Intra) coding structure compared to JEM 7.0. We need to optimize context modeling for additional coding performance enhancement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.3A
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• pp.157-162
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• 2012

In this paper, we propose a new intra mode coding method using the candidate mode table. In the conventional HEVC, if the predicted most probable mode (MPM) is not same with the current prediction mode, the current prediction mode is encoded using the fixed length code (FLC). However, since a large number of modes are used in HEVC, the codeword length of FLC gets longer. In this paper, we generate the candidate mode table from neighboring blocks and encode the obtained intra mode index using Golomb-Rice code instead of FLC, when the predicted MPM is not identical to the current mode. From the experiment, we verified that the proposed method reduces the BD-rate by 0.5% on average, compared to the HEVC intra mode coding method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.552-555
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• 2007

지상파 DMB등에서 많이 사용하고 있는 기술은 H.264이다. 이 H.264는 적은 비트율에 비하여 고해상도의 영상을 만들어 낸다. 이런 손실압축을 하기 위해서 인트라와 인터등과 같은 전처리 과정과 DCT(Discrete Cosine Transform), 양자화 등등이 존재하지만 H.264에서 실제로 압축이 되는 부분은 엔트로피코딩이다. H.264에서는 Exp-Golomb과 CAVLC(Context-Adaptive Variable Length Coding), CABAC(Context-Adaptive Binary Arithmetic Coding) 세 가지를 지원하고 있다. 이중 CAVLC는 테이블을 기반으로한 압축기법을 사용한다. 테이블을 이용할 때는 코드워드의 길이와 값을 비교하는 방식을 사용하게 된다. 이는 수 많은 메모리 접속으로 인한 전력소모와 연산지연을 가져온다. 본 논문에서는 전송된 비트스트림에서 데이터를 찾을 때 코드워드의 길이와 값을 테이블에 비교해서 찾지 않고 테이블에 존재하는 규칙을 수식화 하여 찾을 수 있도록 하였다. 이는 최초 '1'이 나올때까지의 '0'의 개수와 그 이후 존재하는 코드의 값을 이용하여서 각 단계에 필요한 데이터를 추출해 낸다. 위와 같은 알고리즘을 이용하여 VHDL언어로 설계하였다.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.3
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• pp.197-203
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• 2009

Finite field arithmetic is very important in the area of cryptographic applications and coding theory, and it is efficient to use normal bases in hardware implementation. Using the fact that $GF(2^{mk})$ having a type-I optimal normal basis becomes the extension field of $GF(2^m)$, we, in this paper, propose a new serial multiplier which reduce the critical XOR path delay of the best known Reyhani-Masoleh and Hasan's serial multiplier by 25% and the number of XOR gates of Kwon et al.'s multiplier by 2 based on the Reyhani-Masoleh and Hasan's serial multiplier for type-I optimal normal basis.

• The KIPS Transactions:PartB
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• v.8B no.4
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• pp.403-410
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• 2001

물체의 형상을 부호화하기 위한 베이스라인기반 기법을 개선하였다. 베이스라인 기반 기법은 2차원인 물체의 형상 데이터를 전환점(turning point)과 기준선(Baseline)으로 부터의 거리값으로 부호화하는 방식이다. 즉, 가로나 세로의 한 방향의 거리 값과 다른 방향의 전환점을 부호화하는 방식이다. 본 논문에서는 기존의 베이스라인 기반 기법의 성능을 개선하기 위한 방법을 제안하였다. 첫 번째 방법은 허용 왜곡과 비트율을 판단하여 가로나 세로로 기준점의 방향을 변화시킴으로서 부호화해야하는 점들과 전환점들의 개수를 감소시켜서 압축률을 높이는 것이다. 두 번째 방법은 기존의 부표본화에서 사용된 왜곡을 판단보다 더 세밀하게 판단하여 더 많은 종류의 부표본화를 가능케 함으로써 압축률을 높이는 방법이다. 제안하는 방법이 기존의 베이스라인 기반 부호화와 MPEG-4에서 채택하고 있는 CAE(Context-based Arithmetic Encoding)와 비교해 보았을 때 보다 우수한 성능을 보임을 모의실험을 통해 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.34-40
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• 2010

This paper proposes an efficient CABAC encoder to reduce syntax element storage in H.264/AVC entropy coding. In the proposed architecture, all blocks are designed in dedicated hardware, so it performs fast processing without programmable processors. Context modeler of CABAC encoder requires the neighbor block data. However it requires impractically huge memory size if the neighbor block data is directly stored without proper processing. Therefore, this paper proposes an effective method of storing the neighbor block data to decrease memory size. The proposed CABAC encoder has 35,463 gates in 0.18um standard cell library. It operates at maximum speed of 180MHz and its throughput is about 1 cycle per input symbol.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.1
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• pp.27-34
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• 2021

In this paper, we propose a copyright protection scheme for real-time streaming of HEVC(High Efficiency Video Coding) based realistic content. Previous research uses encryption and modular operation for copyright pre-protection and copyright post-protection, which causes delays in ultra high resolution video. The proposed scheme maximizes parallelism by using thread pool based DRM(Digital Rights Management) packaging with only HEVC's CABAC(Context Adaptive Binary Arithmetic Coding) codec and GPU based high-speed bit operation(XOR), thus enabling real-time copyright protection. As a result of comparing this scheme with previous research at three resolutions, PSNR showed an average of 8 times higher performance, and the process speed showed an average of 18 times difference. In addition, as a result of comparing the robustness of the forensic mark, the filter and noise attack, which showed the largest and smallest difference, with a 27-fold difference in recompression attacks, showed an 8-fold difference.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.2
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• pp.124-130
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• 2005

In this paper, low-power design and implementation techniques for DWT(Discrete Wavelet Transform) of the JPEG2000 compression are proposed. In DWT block of the JPEG2000, linear phase 9 tap and 7 tap filters are used. For low-power implementation of those filters, processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized. Proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of the binary values of filter coefficient. Finally, in third block, multiplied values are output and stored in flip-flop train. For comparison of the implementation area and power dissipation, proposed and conventional structures are implemented by using Verilog-HDL coding. In simulation, it is shown that 53.1% of the implementation area can be reduced comparison with those of the conventional structure.

• Journal of IKEEE
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• v.19 no.2
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• pp.254-259
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• 2015

CABAC is a context-based adaptive binary arithmetic coding method. It increases the encoding efficiency by updating the probability based on the information of the previously coded symbols. Context modeler is a core block of CABAC, which designs a probability model according to the symbol considering statistical correlations. In this paper, an efficient hardware architecture of CABAC context modeler is proposed. The proposed context modeler was designed in Verilog HDL and it was implemented in 0.18 um technology. Its gate count is 29,832 gates including memory. Its operating speed and throughput are 200 MHz and 200 Mbin/s, respectively.