• 제목/요약/키워드: bias voltage

검색결과 1,264건 처리시간 0.03초

나시콘 전류검출형 NO2 센서의 성능개선 (Improvement of Sensing Performance on Nasicon Amperometric NO2 Sensors)

  • 김귀열
    • 한국전기전자재료학회논문지
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    • 제20권10호
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    • pp.912-917
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    • 2007
  • Many electrochemical power devices such as solid state batteries and solid oxide fuel cell have been studied and developed for solving energy and environmental problems. An amperometric gas sensor usually generates sensing signal of electric current along the proportion of the concentration of target gas under the condition of limiting current. For narrow variations of gas concentration, the amperometric gas sensor can show higher precision than a potentiometric gas sensor does. In additional, cross sensitivities to interfering gases can possibly be mitigated by choosing applied voltage and electrode materials properly. In order to improve the sensitivity to $NO_2$, the device was attached with Au reference electrode to form the amperometric gas sensor device with three electrodes. With the fixed bias voltage being applied between the sensing and counter electrodes, the current between the sensing and reference electrodes was measured as a sensing signal. The response to $NO_2$ gas was obviously enhanced and suppressed with a positive bias, respectively, while the reverse current occurred with a negative bias. The way to enhance the sensitivity of $NO_2$ gas sensor was thus realized. It was shown that the response to $NO_2$ gas could be enhanced sensitivity by changing the bias voltage.

수평구동형 정전반발력 마이크로액추에이터 (Laterally-Driven Electrostatic Repulsive-Force Microactuator)

  • 이기방;조영호
    • 대한기계학회논문집A
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    • 제25권3호
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    • pp.424-433
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    • 2001
  • We present a new electrostatic repulsive-force microactuator using a lateral repulsive force induced by an asymmetric distribution of electrostatic field. The lateral repulsive force has been characterized by a simple analytical equation, derived from a finite element simulation. A set of repulsive force polysilicon microactuators has been designed and fabricated by a 4-mask surface-micromachining process. Static and dynamic micromechanical behavior of the fabricated microactuators has been measured at the atmospheric pressure for a varying bias voltage. The static displacement of the fabricated microactuator, proportional to the square of the DC bias voltage, is obtained as 1.27 $\mu\textrm{m}$ for the DC bias voltage of 140V. The resonant frequency of the repulsive-force microactuator increases from 11.7 kHz to 12.7 kHz when the DC bias voltage increases from 60V to 140V. The measured quality-factor varies from 12 to 13 for the bias volatge range of 60V∼140V. The characteristics of the electrostatic repulsive-force have been discussed and compared and compared with those of the conventional electrostatic attractive-force.

Low Phase Noise LC-VCO with Active Source Degeneration

  • Nguyen, D.B. Yen;Ko, Young-Hun;Yun, Seok-Ju;Han, Seok-Kyun;Lee, Sang-Gug
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제13권3호
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    • pp.207-212
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    • 2013
  • A new CMOS voltage-bias differential LC voltage-controlled oscillator (LC-VCO) with active source degeneration is proposed. The proposed degeneration technique preserves the quality factor of the LC-tank which leads to improvement in phase noise of VCO oscillators. The proposed VCO shows the high figure of merit (FOM) with large tuning range, low power, and small chip size compared to those of conventional voltage-bias differential LC-VCO. The proposed VCO implemented in 0.18-${\mu}m$ CMOS shows the phase noise of -118 dBc/Hz at 1 MHz offset oscillating at 5.03 GHz, tuning range of 12%, occupies 0.15 $mm^2$ of chip area while dissipating 1.44 mW from 0.8 V supply.

Multitarget Bias Cosputter증착에 의한 $CoSi_2$층의 저온정합성장 및 상전이에 관한 연구 (A Study on the Low Temperature Epitaxial Growth of $CoSi_2$ Layer by Multitarget Bias cosputter Deposition and Phase Sequence)

  • 박상욱;최정동;곽준섭;지응준;백홍구
    • 한국재료학회지
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    • 제4권1호
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    • pp.9-23
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    • 1994
  • Multitarget bias cosputter deposition(MBCD)에 의해 저온($200^{\circ}C$)에서 NaCI(100)상에 정합$CoSi_2$를 성장시켰다. X-선회절과 투과전자현미경에 의해 증착온도와 기판 bias전압에 따른 각각 silicide의 상전이와 결정성을 관찰하였다. Metal induced crystallization(MIC) 과 self bias 효과에 의해 $200^{\circ}C$에서 기판전압을 인가하지 않은 경우에도 결정질 Si이 성장하였다. MIC현상을 이론 및 실험적으로 고찰하였다. 관찰된 상전이는 $Co_2Si \to CoSi \to Cosi_2$로서 유효생성열법칙에 의해 예측된 상전이와 일치하였다. 기판 bias전압 인가시 발생한 이온충돌에 의한 충돌연쇄혼합(collisional cascade mixing), 성장박막 표면의 in situ cleaning, 핵생성처(nucleation site)이 증가로 인하여 상전이, CoSi(111)우선방위, 결정성은 증착온도에 비해 기판bias전압에 더 큰 영향을 받았다. $200^{\circ}C$에서 기판 bias전압을 증가시킴에 따라 이온충돌에 의한 결정입성장이 관찰되었으며, 이를 이온충독파괴(ion bombardment dissociation)모델에 의해 해석하였다. $200^{\circ}C$에서의 기판 bias전압증가에 따른 결정성변화를 정량적으로 고찰하기 위해 Langmuir탐침을 이용하여 $E_{Ar},\; \alpha(V_s)$를 계산하였다.

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Bias 전압에 따른 ZnO:Al 투명전도막의 전기적 특성 (Substrate Bias Voltage Dependence of Electrical Properties for ZnO:Al Film by DC Magnetron Sputtering)

  • 박강일;김병섭;임동건;이수호;곽동주
    • 한국전기전자재료학회논문지
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    • 제17권7호
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    • pp.738-746
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    • 2004
  • Recently zinc oxide(ZnO) has emerged as one of the most promising transparent conducting films with a strong demand of low cost and high performance optoelectronic devices, ZnO film has many advantages such as high chemical and mechanical stabilities, and abundance in nature. In this paper, in order to obtain the excellent transparent conducting film with low resistivity and high optical transmittance for Plasma Display Pannel(PDP), aluminium doped zinc oxide films were deposited on Corning glass substrate by dc magnetron sputtering method. The effects of the discharge power and doping amounts of $Al_2$$O_3$ on the electrical and optical properties were investigated experimentally. Particularly in order to lower the electrical resistivity, positive and negative bias voltages were applied on the substrate, and the effect of bias voltage on the electrical properties of ZnO:Al thin film were also studied and discussed. Films with lowest resistivity of $4.3 \times 10 ^{-4} \Omega-cm$ and good transmittance of 91.46 % have been achieved for the films deposited at 1 mtorr, $400^{\circ}C$, 40 W, Al content of 2 wt% with a substrate bias of +30 V for about 800 nm in film thickness.

탄소 나노 튜브의 수직 배향에 대한 바이어스 인가 전압의 효과 (Effect of the Applied Bias Voltage on the Formation of Vertically Well-Aligned Carbon Nanotubes)

  • 김성훈
    • 한국재료학회지
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    • 제13권7호
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    • pp.415-419
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    • 2003
  • Carbon nanotubes were formed on silicon substrate using microwave plasma-enhanced chemical vapor deposition method. The possibility of carbon nanotubes formation was related to the thickness of nickel catalyst. The growth behavior of carbon nanotubes under the identical thickness of nickel catalyst was strongly dependent on the magnitude of the applied bias voltage. High negative bias voltage (-400 V) gave the vertically well-aligned carbon nanotubes. The vertically well-aligned carbon nanotubes have the multi-walled structure with nickel catalyst at the end position of the nanotubes.

a-Si Gate Driver with Alternating Gate Bias to Pull-Down TFTs

  • Kim, Byeong-Hoon;Pi, Jae-Eun;Oh, Min-Woo;Tao, Ren;Oh, Hwan-Sool;Park, Kee-Chan
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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    • pp.1243-1246
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    • 2009
  • A novel a-Si TFT integrated gate driver circuit which suppresses the threshold voltage shift due to prolonged positive gate bias to pull-down TFTs, is reported. Negative gate-to-drain bias is applied alternately to the pull-down TFTs to recover the threshold voltage shift. Consequently, the stability of the circuit has been improved considerably.

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마이크로 웨이브를 이용한 탄소나노튜브 성장시 바이어스 전압의 효자 (Influence of bias voltage on properties of carbon nanotubes prepared by MPECVD)

  • 최성헌;이재형;양종석;박대희
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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    • pp.1440-1441
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    • 2006
  • In this study, we synthesized CNTs(carbon nanotubes) on the glass substrate by microwave plasma enhanced chemical vapor deposition (MPECVD), Effect of bias voltage on the grown behavior and morphology of CNTs were investigated. Recently, it has been proposed that aligned CNTs can also be achieved by the application of electric bias to the substrate during growth, the first time reported the bias effect such that the nanotube alignment occurred only when a positive bias was applied to the substrate whereas no aligned growth occurred under a negative bias and no tube growth was observed without bias. On the country, several researchers reported some different observations that aligned nanotubes could also be grown under negative substrate biases. This discrepancy as for the effect of positive and negative bias may indicate that the bias effect is not fully understood yet. The glass and Si wafers were first deposited with TiN buffer layer by r.f sputtering method, and then Ni catalyst same method, The thickness of TiN and Ni layer were 200 nm and 60 nm, respectively. The main process parameters include the substrate bias (0 to - 300 V), and deposition pressure (8 to 20 torr).

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대기압 플라즈마 발생시 인가전압의 상승시간에 따른 영향 (Effect of Rise Time of a Pulse Bias Voltage on Atmospheric Plasma Generation)

  • 김재혁;진상일;김영민
    • 전기학회논문지
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    • 제57권7호
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    • pp.1218-1222
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    • 2008
  • We investigate the effect of rise time of a pulse bias voltage on atmospheric plasma generation. With the faster rise time of the pulse bias, the glow discharge appears to be more uniformly generated along the electrodes. I-V measurement confirms that higher loading power can be obtained using the faster rise time. A new understanding for atmospheric plasma generation at a micro-gap electrode is suggested.

Temperature Stable Current Source Using Simple Self-Bias Circuit

  • Choi, Jin-Ho
    • Journal of information and communication convergence engineering
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    • 제7권2호
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    • pp.215-218
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    • 2009
  • In this paper, temperature stable current and voltage references using simple CMOS bias circuit are proposed. To obtain temperature stable characteristics of bias circuit a bandgap reference concept is used in a conventional circuit. The parasitic bipolar transistors or MOS transistors having different threshold voltage are required in a bandgap reference. Thereby the chip area increase or the extra CMOS process is required compared to a standard CMOS process. The proposed reference circuit can be integrated on a single chip by a standard CMOS process without the extra CMOS process. From the simulation results, the reference current variation is less than ${\pm}$0.44% over a temperature range from - $20^{\circ}C$ to $80^{\circ}C$. And the voltage variation is from - 0.02% to 0.1%.