• JSTS:Journal of Semiconductor Technology and Science
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• 제3권2호
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• pp.83-88
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• 2003

The reset operation of a CCD image sensor was improved using charge trapping of a MOS structure to realize a loe voltage driving. A DC bias generating circuit was added to the reset structure which sets reference voltage and holds the signal charge to be detected. The generated DC bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2V to 5.5V, which is suitable for controlling the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole-Frenkel conduction and Fowler-Nordheim conduction. A CCD image sensor with $492(H){\;}{\times}{\;}510(V)$ pixels adopting this structure showed complete reset operation with the driving voltage of 3.0V. The resolution chart taken with the image sensor shows no image flow to the illumination of 30 lux, even in the driving voltage of 3.0V.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2018년도 추계학술대회
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• pp.35-38
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• 2018

본 논문에서는 DC 유형의 에너지 하베스팅을 위한 저전력 MPPT 인터페이스 회로를 설계하였다. 제안된 회로는 크게 MPPT controller, bias generator, voltage detector로 구성된다. MPPT controller는 schmitt trigger로 구성된 MPG(MPPT Pulse Generator)와 에너지 유형(빛, 열)에 따라 동작하는 logic gate와 sample/hold 회로로 구성된다. Bias generator는 beta multiplier 구조를 적용하여 설계되었으며, voltage detector는 bulk-driven comparator와 2단 buffer를 이용하여 설계되었다. 제안된 회로는 $0.35{\mu}m$ CMOS 공정으로 설계하였다. 모의실험 결과 설계된 회로는 3V 이내의 입력전압에서 100nA보다 작은 전류를 소모하며, 최대 전력효율은 99.7%이다. 설계된 회로의 칩 면적은 $1151{\mu}m{\times}940{\mu}m$이다.

• 한국콘텐츠학회논문지
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• 제6권3호
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• pp.38-45
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• 2006

본 논문은 LCD driver IC의 전송선 당 데이터 전송률을 2배로 하기 위한 이중 저전압 차동신호 전송 (DLVDS) 회로를 제안한다. 제안된 회로에서는 2-비트 데이터를 하나의 송신기에서 입력 받고, 2-비트 데이터를 듀얼레벨을 갖는 차동신호로 전송한다. 따라서 기존의 저전압 차동신호 전송기법(LVDS)의 특징을 유지하면서 2-비트 데이터를 2개의 전송선을 통하여 전송할 수 있다. 제안된 송신기는 전류원 피드백 회로를 이용하여 출력의 공통모드 바이어스 흔들림을 보상했다. 그리하여 기존의 회로의 입력 바이어스와 기준 바이어스 전압 차이로 출력의 공통모드 바이어스 흔들림이 발생하는 문제가 해결되었다. 수신기에서는 디코드 회로를 통해 원래의 2-비트 입력 데이터를 복원할 수 있다. 제안된 회로는 $0.25{\mu}m$ CMOS 공정으로 설계하였고, 시뮬레이션 결과 1-Gbps/2-line의 전송률을 갖고, 2.5V의 전원에서 35-mW의 전력소모를 나타냈다.

• 전기화학회지
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• 제6권4호
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• pp.261-265
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• 2003

박막전지의 제조공정 중 열처리 공정은 많은 문제점들을 가지고 있다. 본 연구에서는 열처리 공정 없이 박막의 구조변화를 유발하는 바이어스 스퍼터링(Bias sputtering) 방법으로 $LiCoO_2$ 양극 활물질 박막을 제조하여 그 특성을 고찰하였다. 제조된 박막은 다양한 분석 방법을 이용하여 결정구조, 표면형상, 방전용량을 관찰하였다, 제조된 $LiCoO_2$양극활물질 박막 중 -50 V의 기판 바이어스 전압$(substrate\;bias\;voltage:\;V_b)$을 인가하여 제조된 $LiCoO_2$ 양극 활물질 박막에서 약 $60{\mu}Ah/cm^2{\mu}m.$의 초기 방전 용량을 가짐을 확인하였다. 본 연구는 열처리 공정 없이도 박막전지의 양극활물질로서 $LiCoO_2$ 박막을 사용할 수 있음을 알 수 있었다.

• 전기학회논문지
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• 제56권12호
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• pp.2189-2195
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• 2007

In this paper, we propose a newly developed selective reset waveform of a ac PDP using the wide erase pulse technique with the control of address bias voltage. Although it is generally understood that the wide pulse erasing methode shows the narrow driving margin in an opposite discharge type ac PDP, we could obtain a moderate driving margin in a 3-electrode surface discharge type ac PDP. The obtained driving margin shows a strong dependency on the sustain voltage and the address bias voltage. The lower the sustain and the address bias voltage, the wider the driving margin. The pulse width of the proposed waveform is only $10{\mu}s$, which gives additional time to the sustain period, hence increases the brightness. The brightness and contrast ratio increase about 20% together comparing to the conventional ramp type selective reset waveform with the driving scheme of 10 subfield ADS method. The driving margin was measured with the line by line addressed pattern on the white test panel of 2inch diagonal size and the discharge gas was Ne+Xe4%, 400torr.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.31-32
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• 2007

Built-in voltage in organic light-emitting diodes was studied using modulated photocurrent technique ambient conditions. A device was made with a structure of anode/$Alq_3$/cathode to study a built-in voltage. An ITO was used as an anode, and $Li_2O$/Al was used as a cathode. From the bias voltage-dependent photocurrent, built-in voltage of the device is determined. The applied bias voltage when the magnitude of modulated photocurrent is zero corresponds to a built-in voltage. Built-in voltage in the device is generated due to a difference of work function of the anode and cathode. It was found that for 0.5nm thick $Li_2O$ layer built-in voltage is the higher than the others. It indicates that a very thin alkaline metal compound $Li_2O$ lowers an electron barrier height.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.485-488
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• 1999

In this paper, the effects of back-gate bias on n-channel SOI MOSFETs has been systematically investigated. Back-gate surface is accumulated when negative bias is applied. It is found that the driving current ability of SOI MOSFETs is reduced because the threshold voltage and subthreshold slope are increased and transconductance is decreased due to the hole accumulation in Si body.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.239-244
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• 2017

We experimentally investigate the physical mechanism for asymmetrical degradation in amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) under simultaneous gate and drain bias stresses. The transfer curves exhibit an asymmetrical negative shift after the application of gate-to-source ($V_{GS}$) and drain-to-source ($V_{DS}$) bias stresses of ($V_{GS}=24V$, $V_{DS}=15.9V$) and ($V_{GS}=22V$, $V_{DS}=20V$), but the asymmetrical degradation is more significant after the bias stress ($V_{GS}$, $V_{DS}$) of (22 V, 20 V) nevertheless the vertical electric field at the source is higher under the bias stress ($V_{GS}$, $V_{DS}$) of (24 V, 15.9 V) than (22 V, 20 V). By using the modified external load resistance method, we extract the source contact resistance ($R_S$) and the voltage drop at $R_S$ ($V_{S,\;drop}$) in the fabricated a-IGZO TFT under both bias stresses. A significantly higher RS and $V_{S,\;drop}$ are extracted under the bias stress ($V_{GS}$, $V_{DS}$) of (22 V, 20V) than (24 V, 15.9 V), which implies that the high horizontal electric field across the source contact due to the large voltage drop at the reverse biased Schottky junction is the dominant physical mechanism causing the asymmetrical degradation of a-IGZO TFTs under simultaneous gate and drain bias stresses.

• 한국표면공학회지
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• 제31권6호
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• pp.317-324
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• 1998

TiN and TiCN films were deposited on the high speed steel by Cathode Arc Ion Plating(CAIP) Process to investigate the tool life extension effect. The experiment variables were bias voltage and deposit time for the TiN coating and reactive gas flow rate ($CH_4:N_2$) under fixing deposit pressure, are current, bias voltage for the TiCN coating respectively. The micro structure and mechanical properties were investigated and compared for among the coating conditions using various methods and machining practice.

• Journal of information and communication convergence engineering
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• 제7권1호
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• pp.57-61
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• 2009

This paper has presented the subthreshold current model of FinFET using the potential variation in the doped channel based on the analytical solution of three dimensional Poisson's equation. The model has been verified by the comparison with the data from 3D numerical device simulator. The variation of subthreshold current with front and back gate bias has been studied. The variation of subthreshold swing and threshold voltage with front and back gate bias has been investigated.