• Journal of the Korean Society of Safety
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• v.25 no.3
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• pp.15-21
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• 2010

A differential case equipped with LSD(limited slip differential) has several advantages over a normal type for rear wheel drive vehicles. Specially, the torque distribution can be done between left and right drive wheel in the state of limited slip differential. Also although LSD types are very various according to operating type, medium and torque distribution, a multi-clutch type is generally applied to rear wheel drive vehicles. So, this study presents the analysis of design parameters for development of a friction plate for multi-clutch type LSD using vehicle road test, the simulation of analytical model and the development of vehicle dynamics model by a benchmark product. According to this investigation, the design parameters which are pre-load of coil spring, friction plate and contact area quantity, friction coefficient and TBR(torque bias ratio) for a friction plate are derived from experiment and simulation and consequently, vehicle dynamics model has been constructed for the development of friction plate for multi-clutch type LSD.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1325-1331
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• 1996

In this paper, a new current-memory circuit is proposed that reduces the clock feedthrough(CFT) error voltage causing total harmonic distortion(THD) increment in switched-current(SI) systems. Using PMOS transistor in CMOS complementary, the proposed one reduces output distortion current due to the CFT errorvoltage. A proposed current-memory is designed using a 1.2.mu.m CMOS process anda 1MHz sinusoidal signal having a 68.mu.A amplitude current is applied as input (sampling frequency:20MHz). It hasbeen shown from the simulation that the output distortion current effected by the CFT error voltage is reduced by approximately 10 times the error voltage of conventional one, THD is -57dB in case ofappling 1kHz frequency input signalwith 0.5 peak signal-to-bias current ratio.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.351.1-351.1
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• 2014

In this study, we prepared the solution-based In-Ga-Zn oxide thin film transistors (IGZO TFTs) of multistacked active layer and characterized the gate bias instability by measuring the change in threshold voltage caused by stacking. The solutions for IGZO active layer were prepared by In:Zn=1:1 mole ratio and the ratio of Ga was changed from 20% to 30%. The TFTs with multistacked active layer was fabricated by stacking single, double and triple layers from the prepared solutions. As the number of active layer increases, the saturation mobility shows the value of 1.2, 0.8 and 0.6 (). The electrical properties have the tendency such as decreasing. However when gate bias VG=10 V is forced to gate electrode for 3000 s, the threshold voltage shift was decreased from 4.74 V to 1.27 V. Because the interface is formed between the each layers and this affected the current path to reduce the electrical performances. But the uniformity of active layer was improved by stacking active layer with filling the hole formed during pre-baking so the stability of device was improved. These results suggest that the deposition of multistacked active layer improve the stability of the device.

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.867-869
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• 1999

In this study, $SrBi_{2}Ta_{2}O_{9}$(SBT) thin films were etched as a function of $SF_6$/Ar gas mixing ratio in magnetically enhanced inductively coupled plasma(MEICP) system fer a fixed rf power, dc-bias voltage, and chamber pressure. The etch rate of SBT thin film was $1500{\AA}/min$ and the selectivities of photoresist (PR) and $SiO_2$ to SBT thin film were 0.48 and 0.62, respectively when the samples were etched at a rf power of 600W, a dc-bias voltage of -150V, a chamber pressure of 10 mTorr and a gas mixing ratio of $SF_6/(SF_6+A)$=0.1. In order to examine the chemical reactions on the etched surface, X-ray photoelectron spectroscopy(XPS) and secondary ion mass spectrometry(SIMS) were done.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.43 no.1
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• pp.88-95
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• 2015

This paper considers the effects of propellant mixture ratio and loading errors on the performance of a liquid rocket. Propellant residuals generated by error sources are analyzed for a launch vehicle model whose first stage consists of a cluster rocket of four 75-tonf class engines using a statistical Monte-Carlo approach and then the optimal fuel biases minimizing residuals are computed. The results are validated through comparison with analytic method using approximate formula, which have been applied for other space launch vehicles.

• Journal of the Korean institute of surface engineering
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• v.39 no.6
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• pp.263-267
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• 2006

As technology advances, there is a demand for development of hard solid lubricant coating. (Ti, Cr, Zr)N-$MoS_2$ films were deposited on AISI H13 tool steel substrate by co-deposition of $MoS_2$ with (Ti, Cr, Zr)N using a D.C. magnetron sputtering process. The influence of the $N_2Ar$ gas ratio, the amount of $MoS_2$ in the films and the bias voltage on the mechanical and structural properties of the films were investigated. The highest hardness level was observed at the $N_2/Ar$ gas ratio of 0.3. Hardness of the films did not change much with the increase of the $MoS_2$ content in the films. As the substrate bias potential was increased, hardness level of the film reached maximum at -150 V. Surface morphology of these films indicated that high hardness was attributed to the fine dome structure.

• Journal of Astronomy and Space Sciences
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• v.26 no.3
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• pp.305-316
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• 2009

In this study, we suggest an empirical forecast of CIR (Corotating Interaction Regions) and geomagnetic storm based on the information of coronal holes (CH). For this we used CH data obtained from He I $10830{\AA}$ maps at National Solar Observatory-Kitt Peak from January 1996 to November 2003 and the CIR and storm data that Choi et al. (2009) identified. Considering the relationship among coronal holes, CIRs, and geomagnetic storms (Choi et al. 2009), we propose the criteria for geoeffective coronal holes; the center of CH is located between $N40^{\circ}$ and $S40^{\circ}$ and between $E40^{\circ}$ and $W20^{\circ}$, and its area in percentage of solar hemispheric area is larger than the following areas: (1) case 1: 0.36%, (2) case 2: 0.66%, (3) case 3: 0.36% for 1996-2000, and 0.66% for 2001-2003. Then we present contingency tables between prediction and observation for three cases and their dependence on solar cycle phase. From the contingency tables, we determined several statistical parameters for forecast evaluation such as PODy (the probability of detection yes), FAR (the false alarm ratio), Bias (the ratio of "yes" predictions to "yes" observations) and CSI (critical success index). Considering the importance of PODy and CSI, we found that the best criterion is case 3; CH-CIR: PODy=0.77, FAR=0.66, Bias=2.28, CSI=0.30. CH-storm: PODy=0.81, FAR=0.84, Bias=5.00, CSI=0.16. It is also found that the parameters after the solar maximum are much better than those before the solar maximum. Our results show that the forecasting of CIR based on coronal hole information is meaningful but the forecast of goemagnetic storm is challenging.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.12
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• pp.2189-2195
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• 2007

In this paper, we propose a newly developed selective reset waveform of a ac PDP using the wide erase pulse technique with the control of address bias voltage. Although it is generally understood that the wide pulse erasing methode shows the narrow driving margin in an opposite discharge type ac PDP, we could obtain a moderate driving margin in a 3-electrode surface discharge type ac PDP. The obtained driving margin shows a strong dependency on the sustain voltage and the address bias voltage. The lower the sustain and the address bias voltage, the wider the driving margin. The pulse width of the proposed waveform is only $10{\mu}s$, which gives additional time to the sustain period, hence increases the brightness. The brightness and contrast ratio increase about 20% together comparing to the conventional ramp type selective reset waveform with the driving scheme of 10 subfield ADS method. The driving margin was measured with the line by line addressed pattern on the white test panel of 2inch diagonal size and the discharge gas was Ne+Xe4%, 400torr.

• Journal of the Korean institute of surface engineering
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• v.32 no.2
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• pp.93-99
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• 1999

Surface polymer layer formed on the silicon wafer during the oxide overetching using $C_4F_8$/ helicon wave plasmas and their characteristics were investigated using spectroscopic elipsometry, X-ray photoelectron spectroscopy, and secondary ion mass spectrometry. Overetch percentage and dc-self bias voltage were varied to investigate the effects on the characteristics of the polymers remaining on the overetched silicon surface. The increase of bias voltage from -80 volts to -120 volts increased the C/F ratio and carbon bondings such as C-C, $C-CF_x$/, and C-Si in the polymer while reducing the thickness of the polymer layer. However, the increase of the overetch percentage from 50% to 100% did not change the composition of the polymer layer and the carbon bondings in the polymer layer remained same even though it increased the polymer thickness. The polymer layer formed at the higher dc-self bias voltage was more difficult to be removed by the following various post-etch treatments compared to that formed at the longer overetch percentage.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2013.05a
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• pp.154-154
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• 2013

In this work, we investigated the characteristics and the effects of light on the negative gate bias stress stability (NBS) in high mobility polycrystalline IGO TFTs. IGO TFT showed a high drain current on/off ratio of ${\sim}10^9$, a field-effect mobility of $114cm^2/Vs$, a threshold voltage of -4V, and a subthresholdslpe(SS) of 0.28V/decade from log($I_{DS}$) vs $V_{GS}$. IGO TFTs showed large negative $V_{TH}$ shift(17V) at light power of $5mW/cm^2$ with negative gate bias stress of -10V for 10000seconds, at a fixed drain voltage ($V_{DS}$) of 0.5V.