• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.6
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• pp.372-376
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• 2018

The effects of off-state bias stress on the characteristics of p-type poly-Si TFT were investigated. To reduce the gate-induced drain leakage (GIDL) current, the off-state bias stress was changed by varying Vgs and Vds. After application of the off-state bias stress, the Vgs causing GIDL current was dramatically increased from 1 to 10 V, and thus, the Vgs margin to turn off the TFT was improved. The on-current and subthreshold swing in the aged TFT was maintained. We performed a technology computer-aided design (TCAD) simulation to describe the aged characteristics. The aged-transfer characteristics were well described by the local charge trapping. The activation energy of the GIDL current was measured for the pristine and aged characteristics. The reduced GIDL current was mainly a thermionic field-emission current.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.4
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• pp.247-249
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• 2016

In this study, we investigated the color change of the normal light gray granite as the high value color granite. By coating the metal catalyst liquid on the surface of granite stone, the metal particles were penetrated into the granite and the color of granite was changed permanently through the annealing treatment. To increase penetration depth into the granite, we used DC (direct current) bias. Two kinds of bias were used such as DC bias and pulse DC bias. And the penetration time was changed as 30 and 60 min. In all cases, the color granite were successfully obtained. Regardless of the catalyst reaction time, the penetration depth was increased by using the bias treatment. We obtained a penetration depth of 21 mm with the DC pulse bias during 60 min.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.1211-1213
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• 2004

In this paper, in other the study shift a degradation and electrical properties on ZnO based grain beurdry layer, we mearured thermally stmulated current. Also the TSC was investigated for understanding of GBL's interfacial carrier shift on bias voltage, bias time, bias temperature. as a result, the two peahs of $p_1$, $p_2$ was observed by conduction of the trapped carrier of border between the oxidation layer and the grains $P_3$ and $P_4$ Peaks observed to the ionization excition excitation in the grain.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.3
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• pp.439-444
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• 2016

The method for extracting the SPICE model parameter of Schottky diode under DC forward bias is proposed. A method for improving the accuracy of the SPICE model parameter at various temperatures is proposed. Three analysis steps according to the magnitude of the current is used in order to extract the parameters effectively. At each analysis step, initial parameters are calculated by using the current-voltage equations and the Levenberg-Marquardt analysis is proceeded. To verify the validity of the proposed method, the SPICE model parameters for the BAT45 and FSV1045 under DC forward bias is extracted. Schottky diode currents obtained from the proposed method shows the average relative error of 6.1% and 9% compared with the measured data for the BAT45 and FSV1045 sample at various temperatures.

• Journal of Power Electronics
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• v.16 no.3
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• pp.960-969
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• 2016

High-power three-level voltage-source converters are widely utilized in high-performance AC drive systems. In several ultra-power instances, the harmonics on the grid side should be reduced through multiple rectifications. A combined harmonic elimination method that includes a dual primary-side series-connected winding transformer and selective harmonic elimination pulse-width modulation is proposed to eliminate low-order current harmonics on the primary and secondary sides of transformers. Through an analysis of the harmonic influence caused by dead time and DC magnetic bias, a synthetic compensation control strategy is presented to minimize the grid-side harmonics in the dual primary side series-connected winding transformer application. Both simulation and experimental results demonstrate that the proposed control strategy can significantly reduce the converter input current harmonics and eliminates the DC magnetic bias in the transformer.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1739-1741
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• 2000

DC current density-voltage and impedance spectroscopy studies have been performed on indium-tin-oxide(ITO)/para-sexiphenyl(6p)/aluminium organic electroluminescent device. The device exhibited a blue color emission, The turn-on voltage of the device is observed at 5V from the current density-voltage measurements. The impedance spectroscopy measurements show that a resonance frequency shift with applied DC bias is observed and a single semi-circle Cole-Cole plot is confirmed. The bias-dependent bulk resistance and bias-independent bulk capacitance is observed.

• Journal of Communications and Networks
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• v.14 no.5
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• pp.540-545
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• 2012

In this paper, the lagged cross-correlation of two probability density functions constructed by kernel density estimation is proposed, and by maximizing the proposed function, adaptive filtering algorithms for supervised and unsupervised training are also introduced. From the results of simulation for blind equalization applications in multipath channels with impulsive and slowly varying direct current (DC) bias noise, it is observed that Gaussian kernel of the proposed algorithm cuts out the large errors due to impulsive noise, and the output affected by the DC bias noise can be effectively controlled by the lag ${\tau}$ intrinsically embedded in the proposed function.

• Current Optics and Photonics
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• v.5 no.2
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• pp.129-133
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• 2021

This study observed the performance of an InAs/GaSb type-II superlattice photodiode with a p-i-n structure for mid-wavelength infrared detection. The 10 ML InAs/10 ML GaSb type-II superlattice photodiode was grown using molecular beam epitaxy. The cutoff wavelength of the manufactured photodiode with Si3N4 passivation on the mesa sidewall was determined to be approximately 5.4 and 5.5 ㎛ at 30 K and 77 K, respectively. At a bias of -50 mV, the dark-current density for the Si3N4-passivated diode was measured to be 7.9 × 10-5 and 1.1 × 10-4 A/㎠ at 77 K and 100 K, respectively. The differential resistance-area product RdA at a bias of -0.15 V was 1481 and 1056 Ω ㎠ at 77 K and 100 K, respectively. The measured detectivity from a blackbody source at 800 K was calculated to be 1.1 × 1010 cm Hz1/2/W at zero bias and 77 K.

• Journal of information and communication convergence engineering
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• v.8 no.1
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• pp.107-111
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• 2010

This paper has presented the dependence of the threshold voltage on back gate bias and drain voltage for FinFET. The FinFET has three gates such as the front gate, side and back gate. Threshold voltage is defined as the front gate bias when drain current is 1 micro ampere as the onset of the turn-on condition. In this paper threshold voltage is investigated into the analytical potential model derived from three dimensional Poisson's equation with the variation of the back gate bias and drain voltage. The threshold voltage of a transistor is one of the key parameters in the design of CMOS circuits. The threshold voltage, which described the degree of short channel effects, has been extensively investigated. As known from the down scaling rules, the threshold voltage has been presented in the case that drain voltage is the 1.0V above, which is set as the maximum supply voltage, and the drain induced barrier lowing(DIBL), drain bias dependent threshold voltage, is obtained using this model.

• Journal of Surface Science and Engineering
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• v.43 no.3
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• pp.154-158
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• 2010

Numerical analysis is done to investigate the effects of pulse bias on the plasma processing characteristics like ion doping and ion nitriding by using fluid dynamic code with a 2D axi-symmetric model. For 10 mTorr of Ar plasma, -1 kV of pulse bias was simulated. Maximum sheath thickness was around 20 mm based on the electric potential profile. The peak electron temperature was about 20 eV, but did not affect the averaged plasma characteristics of the whole chamber. Maximum ion current density incident on the substrate was 200 $A/m^2$ at the center, but was decreased down to 1/10th at radius 100 mm, giving poor radial uniformity.