• Title/Summary/Keyword: bias current

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Comparison of Safety Margin of Shallow Foundation on Weathered Soil Layer According to Design Methods (설계법에 따른 풍화토 지반 얕은기초의 안전여유 비교)

  • Kim, Donggun;Hwang, Huiseok;Yoo, Namjae
    • Journal of the Korean GEO-environmental Society
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    • v.17 no.12
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    • pp.55-64
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    • 2016
  • In this paper bearing capacity and safety margin of shallow foundation on weathered soil ground against shear failure by using current design method of allowable stress design (ASD), load resistance factor design (LRFD) based on reliability analysis and partial safety factor design (PSFD) in Eurocode were estimated and compared to each other. Results of the plate loading test used in construction and design were collected and analysis of probability statistics on soil parameters affecting the bearing capacity of shallow foundation was performed to quantify the uncertainty of them and to investigate the resistance bias factor and covalence of ultimate bearing capacity. For the typical sections of shallow foundation in domestic field as examples, reliability index was obtained by reliability analysis (FORM) and the sensitivity analysis on soil parameters of probability variables was performed to investigate the effect of probability variable on shear failure. From stability analysis for these sections by ASD, LRFD with the target reiability index corresponding to the safety factor used in ASD and PSDF, safety margins were estimated respectively and compared.

Properties of Pt/${Al_0.33}{Ga_0.67}N$ Schottky Type UV Photo-detector (Pt 전극을 이용한 ${Al_0.33}{Ga_0.67}N$ 쇼트키형 자외선 수광소자의 동작특성)

  • 신상훈;정영로;이재훈;이용현;이명복;이정희;이인환;한윤봉;함성호
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.7
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    • pp.486-493
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    • 2003
  • Schottky type A $l_{0.33}$G $a_{0.67}$N ultraviolet photodetectors were fabricated on the MOCVD grown AlGaN/ $n^{+}$-GaN and AlGaN/AlGaN interlayer/ $n^{+}$-GaN structures. The grown layers have the carrier concentrations of -$10^{18}$, and the mobilities were 236 and 269 $\textrm{cm}^2$/V.s, respectively. After mesa etching by ICP etching system, the Si3N4 layer was deposited for passivation between the contacts and Ti/AL/Ni/Au and Pt were deposited for ohmic and Schottky contact, respectively. The fabricated Pt/A $l_{0.33}$G $a_{0.67}$N Schottky diode revealed a leakage current of 1 nA for samples with interlayer and 0.1$\mu\textrm{A}$ for samples without interlayer at a reverse bias of -5 V. In optical measurement, the Pt/A $l_{0.33}$G $a_{0.67}$N diode with interlayer showed a cut-off wavelength of 300 nm, a prominent responsivity of 0.15 A/W at 280 nm and a UV-visible extinction ratio of 1.5x$10^4./TEX>.

An Implementation of Temperature Independent Bias Scheme in Voltage Detector (온도에 무관한 전압검출기의 바이어스 구현)

  • Moon, Jong-Kyu;Kim, Duk-Gyoo
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.39 no.6
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    • pp.34-42
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    • 2002
  • In this paper, we propose a temperature independent the detective voltage source in voltage detector. The value of a detective voltage source is designed to become m times of silicon bandgap voltage at zero absolute temperature. By properly choosing the temperature coefficient of diode, the temperature coefficient of a concave voltage nonlinearities generated by the ${\Delta}V_{BE}$ section of diode between base and emitter of transistors with a different area can be summed with convex nonlinearities the $V_{BE}$ voltage to achieve the near zero temperature coefficient of the detective voltage source. We designed that the value of a detective voltage can be varied by ${\Delta}V_{BE}$, the $V_{BE}$multiplier circuit and resistor. In order to verify the performance of a proposed detective voltage source, we manufactured the voltage detector IC for 1.9V which is fabricated in $6{\mu}m$ Bipolar technology and measured the operating characteristics, the temperature coefficient of a detective voltage. To reduce the deviation of a detective voltage in the IC process step, we introduced a trimming technology, ion implantation and an isotropic etching. In manufactured IC, the detective voltage source could achieve the stable temperature coefficient of 29ppm/$^{\circ}C$ over the temperature range of -30$^{\circ}C$ to 70$^{\circ}C$. The current consumption of a voltage detector constituted by the proposed detective voltage source is $10{\mu}A$ from 1.9V-supply voltage at room temperature.

Fabrication and Evaluation of NMOS Devices (NMOS 소자의 제작 및 평가)

  • 이종덕
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.16 no.4
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    • pp.36-46
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    • 1979
  • Using N_ Ch silicon gate technology . the capacitors and transistors with various dimenssion were fabricated. Although the applied process was somewhat standard the conditions of ion implantation for the gate were varied by changing the implant energies from 30keV to 60keV for B and from 100 keV to 175keV for P . The doses of the implant also changed from 3 $\times$ 10 /$\textrm{cm}^2$ to 5 $\times$ 10 /$\textrm{cm}^2$ for B and from 4$\times$ 10 /$\textrm{cm}^2$ to 7 $\times$ 10 /$\textrm{cm}^2$ for P . The D. C. parameters such as threshold voltage. substrate doping level, the degree of inversion, capacitance. flat band voltage, depletion layer width, gate oxide thickless, surface states, motile charge density, electron mobility. leakage current were evaluated and also compared with the corresponing theoretical values and / or good numbers for application. The threshold voltages measured using curve tracer and C-V plot gave good agreements with the values calculated from SUPREM II which has been developed by Stanford University process group. The threshold vol tapes with back gate bias were used to calculate the change of the substrate doping level. The measured subthreshold slope enabled the prediction of the degree of inversion The D. C. testing results suggest the realized capacitors and transistors are suited for the memory applications.

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A Parametric Study of Pulsed Gamma-ray Detectors Based on Si Epi-Wafer (실리콘 에피-웨이퍼 기반의 펄스감마선 검출센서 최적화 연구)

  • Lee, Nam-Ho;Hwang, Young-Gwan;Jeong, Sang-Hun;Kim, Jong-Yeol;Cho, Young
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.7
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    • pp.1777-1783
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    • 2014
  • In this paper, we designed and fabricated a high-speed semiconductor sensor for use in power control devices and analyzed the characteristics with pulsed radiation tests. At first, radiation sensitive circular Si PIN diodes with various diameters(0.1 mm ~5.0 mm) were designed and fabricated using Si epitaxial wafer, which has a $42{\mu}m$ thick intrinsic layer. The reverse leakage current of the diode with a radius of 2 mm at a reverse bias of 30 V was about 20.4 nA. To investigate the characteristic responses of the developed diodes, the pulsed gamma-radiation tests were performed with the intensity of 4.88E8 rad(Si)/sec. From the test results showing that the output currents and the rising speeds have a linear relationship with the area of the sensors, we decided that the optimal condition took place at a 2 mm diameter. Next, for the selected 2 mm diodes, dose rate tests with a range of 2.47E8 rad(Si)/sec to 6.21E8 rad(Si)/sec were performed. From the results, which showed linear characteristics with the radiation intensity, a large amount of photocurrent over 60mA, and a high speed response under 350ns without saturation, we can conclude that the our developed PIN diode can be a good candidate for the sensor of power control devices.

The surface kinetic properties between $BCl_3/Cl_2$/Ar plasma and $Al_2O_3$ thin film

  • Yang, Xue;Kim, Dong-Pyo;Um, Doo-Seung;Kim, Chang-Il
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.169-169
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    • 2008
  • To keep pace with scaling trends of CMOS technologies, high-k metal oxides are to be introduced. Due to their high permittivity, high-k materials can achieve the required capacitance with stacks of higher physical thickness to reduce the leakage current through the scaled gate oxide, which make it become much more promising materials to instead of $SiO_2$. As further studying on high-k, an understanding of the relation between the etch characteristics of high-k dielectric materials and plasma properties is required for the low damaged removal process to match standard processing procedure. There are some reports on the dry etching of different high-k materials in ICP and ECR plasma with various plasma parameters, such as different gas combinations ($Cl_2$, $Cl_2/BCl_3$, $Cl_2$/Ar, $SF_6$/Ar, and $CH_4/H_2$/Ar etc). Understanding of the complex behavior of particles at surfaces requires detailed knowledge of both macroscopic and microscopic processes that take place; also certain processes depend critically on temperature and gas pressure. The choice of $BCl_3$ as the chemically active gas results from the fact that it is widely used for the etching o the materials covered by the native oxides due to the effective extraction of oxygen in the form of $BCl_xO_y$ compounds. In this study, the surface reactions and the etch rate of $Al_2O_3$ films in $BCl_3/Cl_2$/Ar plasma were investigated in an inductively coupled plasma(ICP) reactor in terms of the gas mixing ratio, RF power, DC bias and chamber pressure. The variations of relative volume densities for the particles were measured with optical emission spectroscopy (OES). The surface imagination was measured by AFM and SEM. The chemical states of film was investigated using X-ray photoelectron spectroscopy (XPS), which confirmed the existence of nonvolatile etch byproducts.

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A Re-configurable 0.8V 10b 60MS/s 19.2mW 0.13um CMOS ADC Operating down to 0.5V (0.5V까지 재구성 가능한 0.8V 10비트 60MS/s 19.2mW 0.13um CMOS A/D 변환기)

  • Lee, Se-Won;Yoo, Si-Wook;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.3
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    • pp.60-68
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    • 2008
  • This work describes a re-configurable 10MS/s to 100MS/s, low-power 10b two-step pipeline ADC operating at a power supply from 0.5V to 1.2V. MOS transistors with a low-threshold voltage are employed partially in the input sampling switches and differential pair of the SHA and MDAC for a proper signal swing margin at a 0.5V supply. The integrated adjustable current reference optimizes the static and dynamic performance of amplifiers at 10b accuracy with a wide range of supply voltages. A signal-isolated layout improves the capacitor mismatch of the MDAC while a switched-bias power-reduction technique reduces the power dissipation of comparators in the flash ADCs. The prototype ADC in a 0.13um CMOS process demonstrates the measured DNL and INL within 0.35LSB and 0.49LSB. The ADC with an active die area of $0.98mm^2$ shows a maximum SNDR and SFDR of 56.0dB and 69.6dB, respectively, and a power consumption of 19.2mW at a nominal condition of 0.8V and 60MS/s.

Study on the way how to make the recruiting Examination of 'Machinery·Metal' Subject in Technical High School. (중등임용시험 '기계·금속' 과목의 출제방안 연구)

  • Choi, Jun-Seop;Lee, Seoung-Won;Kim, Jong-Chan;Jung, Bong-Kyoon;Park, Sang-Jin;Kwon, Cha-Mi
    • 대한공업교육학회지
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    • v.31 no.2
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    • pp.111-127
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    • 2006
  • The purpose of this study is to analyze current recruiting examination and to categorize and construct test item that assess a variety of Mechanic Metal teachers in technical high school for appointing new Mechanic Metal teacher. The future developmental directions in this study are as follows: First, the examination for appointing secondary school new Mechanic Metal Teacher reflects the curriculum of the teacher education and technical high school, must be nomalize. Second, the rational readjustment of the basic necessary subjects for Machinery Metal recruiting examination is required. Third, the Mechanic Metal recruiting examination must prepare the criteria for the domain ratio of presenting problems and improve with level of presenting the question items which demands a knowledge, application and critical thinking. Fourth, in order to avoid the bias of the some subject tendency with committee making questions of different domain, more participation of a committee making questions is required. Fifth, the practical evaluation must be executed by the effective method to be able to make up for the limit of paper and pencil tests Sixth, as the long-term prospect to secure the professionalism of teacher, the recruiting examination of teachers must be carried out with the Machinery and Metal subject, respectively.

Analysis of the Threshold Voltage Instability of Bottom-Gated ZnO TFTs with Low-Frequency Noise Measurements (Low-Frequency Noise 측정을 통한 Bottom-Gated ZnO TFT의 문턱전압 불안정성 연구)

  • Jeong, Kwang-Seok;Kim, Young-Su;Park, Jeong-Gyu;Yang, Seung-Dong;Kim, Yu-Mi;Yun, Ho-Jin;Han, In-Shik;Lee, Hi-Deok;Lee, Ga-Won
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.23 no.7
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    • pp.545-549
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    • 2010
  • Low-frequency noise (1/f noise) has been measured in order to analyze the Vth instability of ZnO TFTs having two different active layer thicknesses of 40 nm and 80 nm. Under electrical stress, it was found that the TFTs with the active layer thickness of 80 nm shows smaller threshold voltage shift (${\Delta}V_{th}$) than those with thickness of 40 nm. However the ${\Delta}V_{th}$ is completely relaxed after the removal of DC stress. In order to investigate the cause of this threshold voltage instability, we accomplished the 1/f noise measurement and found that ZnO TFTs exposed the mobility fluctuation properties, in which the noise level increases as the gate bias rises and the normalized drain current noise level($S_{ID}/{I_D}^2$) of the active layer of thickness 80 nm is smaller than that of active layer thickness of thickness 40 nm. This result means that the 80 nm thickness TFTs have a smaller density of traps. This result correlated with the physical characteristics analysis performmed using XRD, which indicated that the grain size increases when the active layer thickness is made thicker. Consequently, the number of preexisting traps in the device increases with decreasing thickness of the active layer and are related closely to the $V_{th}$ instability under electrical stress.

A Design of Digital CMOS X-ray Image Sensor with $32{\times}32$ Pixel Array Using Photon Counting Type (포톤 계수 방식의 $32{\times}32$ 픽셀 어레이를 갖는 디지털 CMOS X-ray 이미지 센서 설계)

  • Sung, Kwan-Young;Kim, Tae-Ho;Hwang, Yoon-Geum;Jeon, Sung-Chae;Jin, Seung-Oh;Huh, Young;Ha, Pan-Bong;Park, Mu-Hun;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.7
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    • pp.1235-1242
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    • 2008
  • In this paper, x-ray image sensor of photon counting type having a $32{\times}32$ pixel array is designed with $0.18{\mu}m$ triple-well CMOS process. Each pixel of the designed image sensor has an area of loot $100{\times}100\;{\mu}m2$ and is composed of about 400 transistors. It has an open pad of an area of $50{\times}50{\mu}m2$ of CSA(charge Sensitive Amplifier) with x-ray detector through a bump bonding. To reduce layout size, self-biased folded cascode CMOS OP amp is used instead of folded cascode OP amp with voltage bias circuit at each single-pixel CSA, and 15-bit LFSR(Linear Feedback Shift Register) counter clock generator is proposed to remove short pulse which occurs from the clock before and after it enters the counting mode. And it is designed that sensor data can be read out of the sensor column by column using a column address decoder to reduce the maximum current of the CMOS x-ray image sensor in the readout mode.