• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.44-54
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• 2000

In this paper, a design methodology for the frequency-adaptive negative-delay circuit which can be implemented in standard CMOS memory process is proposed. The proposed negative-delay circuit which is a basic type of the analog SMD (synchronous mirror delay) measures the time difference between the input clock period and the target negative delay by utilizing analog behavior and repeats it in the next coming cycle. A new technology that compensates the auxiliary delay related with the output clock in the measure stage differentiates the Proposed method from the conventional method that compensates it in the delay-model stage which comes before the measure stage. A wider negative-delay range especially prominent in the high frequency performance than that in the conventional method can be realized through the proposed technology. In order to implement the wide locking range, a new frequency detector and the method for optimizing the bias condition of the analog circuit are suggested. An application example to the clocking circuits of a DDR SDRAM is simulated and demonstrated in a 0.6 ${\mu}{\textrm}{m}$ n-well double-poly double-metal CMOS technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.880-883
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• 2002

In this paper, we propose the synchronization recovery algorithm which is suitable to wireless multimedia of wireless channel situation which is being used OFDM signaling method. The basic of the suggested clock synchronization. restoration Algorithm is to getting the shock response of channel or getting the multipath strength profile through IFFT after the getting the frequency, response of deducted channel from channel deductor of receiver and to trace the location in the channel energy concentrated area of timing area. And it also analysis the start point of 64-QAM and 16-QAM if the sampling clock offset has the sample of $\pm$1-3, and we identified the occurance of performance deterioration when occures more than 2 samples of offset to compare with star point and BER performance in optimum sampling point result of BER performance checking, and we know that the recovery algorithm proposed algorithm also provide excellent synchronization characteries under frequency, selecting fading channel as result of simulation.

• ETRI Journal
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• v.26 no.6
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• pp.657-660
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• 2004

We propose a fine phase tuner and a rounding processor for a numerically controlled oscillator (NCO), yielding a reduced phase error in generating a digital sine waveform. By using the fine phase tuner presented in this paper, when the ratio of the desired sine wave frequency to the clock frequency is expressed as a fraction, an accurate adjustment in representing the fractional value can be achieved with simple hardware. In addition, the proposed rounding processor reduces the effects of phase truncation on the output spectrum. Logic simulation results of the NCO using these techniques show that the noise spectrum and mean square error (MSE) for eight output bits of a 3.125 MHz sine waveform are reduced by 8.68 dB and 5.5 dB, respectively, compared to those of the truncation method, and 2.38 dB and 0.83 dB, respectively, compared to those of Paul's scheme.

• Journal of Korea Society of Industrial Information Systems
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• v.7 no.3
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• pp.1-8
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• 2002

Modular Multiplication in Galois Field GF(2/sup m/) is a basic operation for many applications, particularly for public key cryptography. This paper presents a new architecture that can process modular multiplication on GF(2/sup m/) per m clock cycles using a cellular automata. Proposed architecture is more efficient in terms of the space and time than that of systolic array. Furthermore it can be efficiently used for the hardware design for exponentiation computation.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1992.04a
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• pp.127-132
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• 1992

To relize the future intelligent robot the development of a special-purpose processor for a coordinate transformation is evidently challenging task. In this case the complexity of a hardware architecture strongly depends on the adopted algorithm. In this paper we have used an inverse kinemetics algorithm based on incremental unit computation method. This method considers the 3-axis articulated robot as the combination of two types of a 2-axis robot: polar robot and 2-axis planar articulated one. For each robot incremental units in the joint and Cartesian spaces are defined. With this approach the calculation of the inverse Jacobian matrix can be realized through a simple combinational logic gate. Futhermore, the incremental computation of the DDA integrator can be used to solve the direct kinematics. We have also designed a hardware architecture to implement the proposed algorithm. The architecture consists of serveral simple unitsl. The operative unit comprises several basic operators and simple data path with a small bit-length. The hardware architecture is realized byusing the EPLD. For the straight-line motion of the KAIST arm we have obtained maximum end effector's speed of 12.6 m/sec by adopting system clock of 8 MHz.

• Journal of Integrative Natural Science
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• v.10 no.1
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• pp.7-13
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• 2017

Neuromedin U receptor 1 is a GPCR protein which binds with the neuropeptide, neuromedin. It is involved in the regulation of feeding and energy homeostasis and related with immune mediated inflammatory diseases like asthma. It plays an important role in maintaining the biological clock and in the regulation of smooth muscle contraction in the gastrointestinal and genitourinary tract. Analysing the structural features of the receptor is crucial in studying the pathophysiology of the diseases related to the receptor important. As the three dimensional structure of the protein is not available, in this study, we have performed the homology modelling of the receptor using 5 different templates. The models were subjected to model validation and two models were selected as optimal. These models could be helpful in analysing the structural features of neuromedin U receptor 1 and their role in disorders related to them.

• The Journal of the Acoustical Society of Korea
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• v.24 no.1
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• pp.11-20
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• 2005

In this paper, we deal with the research about a S/PDIF (Sony Philips Digital Interface) receiver which can operate without PLL (Phase Locked Loop) circuits. Although a S/PDIF receiver is used in most audio devices and audio processors in these days. yet there are only few domestic researches about S/PDIF. Currently used commercial DACs (Digital-to-Analog Converters) which can decode S/PDIF signals, have a PLL circuit inside them. The PLL makes it possible to extract clock information from S/PDIF digital signal and to synchronize a clock signal with input signals. But the PLL circuit makes many diffculties in designing the SOC (System On Chips) of VLSIs (Vew Large Scale Integrated Ciruits) because it is an "analog circuit". We proposed a S/PDIF receiver which doesn't have PLL circuits and only has Pure digital circuits. The key idea of the proposed S/PDIF receiver. is to use the ratio between a 16 MHz basic input clock and S/PDIF signals. After having decoded hundreds thousands S/PDIF inputs, it went to prove that a S/PDIF receiver can be designed with pure digital circuits and without any analog circuits such as PLL circuits. We have confidence that the proposed S/PDIF receiver can be used as an IP (Intellectual Property) for the SOC design of the digital circuits.

• Korean Journal of Cognitive Science
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• v.27 no.4
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• pp.501-539
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• 2016

The human mind is a self-evolving system that develops along a multidimensional hierarchical pathway in response to traumatic stimulus. In absence of trauma, a mind integrated in conflict-free state is called monistic. When the monistic mind responses to a traumatic stimulus, a response polarity forms toward stimulus polarity within the mind, turning it into a bipartite structure. Dialectical interaction between the two opposites, originating from their incompatibility, creates a new third polarity in the upper dimension. Thereby, the mind turns into a trinity structure. When the interaction among the three polarities becomes optimized, the plasticity of the mind gets maximized into the "far-from-equilibrium state," and the function of three polarities is synchronized. Through this recalibration, the mind returns back to its monistic structure. If the mind with the recurred monistic structure responds to another traumatic stimulus, this cycle of hierarchical transformation repeats itself in this cyclical and fractal growth process through synchronization of basic trinity system. Applying this concept to the process of post-traumatic growth (PTG), this paper explores how the mind transforms traumatic experiences into PTG and proposes a 'PTG Clock' that shows a fundamental sequence in the development of the human mind. The PTG Clock consists of seven hierarchical phases, and each of the first six phases has two opposite sub-phases: shocked/numbed, feared/intrusive, paranoid/avoidant, obsessional/explosive, dependent/depressive, and meaningless/searching for meaning. The seventh, the synchronization phase, completes one cycle of the mind's transformation, realizing a grand trinity system, where the mind synchronizes its biological, social, and existential dimensions. At that point, the mind becomes more susceptible to not only the stimulus of its own traumatic experience but also the pain of others. Thereby, the PTG Clock sets out on a journey to another cycle of transformation in higher dimensions. The validity of this transformational process for the PTG Clock will be examined by comparing it to Horowitz's theory of stress response syndrome.

• Journal of IKEEE
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• v.25 no.1
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• pp.156-167
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• 2021

In this paper, we propose a digital transceiver unit design for in-building of 5G optical repeaters that extends the coverage of 5G mobile communication network services and connects to a stable wireless network in a building. The digital transceiver unit for driving the proposed 5G optical repeater is composed of 4 blocks: a signal processing unit, an RF transceiver unit, an optical input/output unit, and a clock generation unit. The signal processing unit plays an important role, such as a combination of a basic operation of the CPRI interface, a 4-channel antenna signal, and response to external control commands. It also transmits and receives high-quality IQ data through the JESD204B interface. CFR and DPD blocks operate to protect the power amplifier. The RF transmitter/receiver converts the RF signal received from the antenna to AD, is transmitted to the signal processing unit through the JESD204B interface, and DA converts the digital signal transmitted from the signal processing unit to the JESD204B interface and transmits the RF signal to the antenna. The optical input/output unit converts an electric signal into an optical signal and transmits it, and converts the optical signal into an electric signal and receives it. The clock generator suppresses jitter of the synchronous clock supplied from the CPRI interface of the optical input/output unit, and supplies a stable synchronous clock to the signal processing unit and the RF transceiver. Before CPRI connection, a local clock is supplied to operate in a CPRI connection ready state. XCZU9CG-2FFVC900I of Xilinx's MPSoC series was used to evaluate the accuracy of the digital transceiver unit for driving the 5G optical repeater proposed in this paper, and Vivado 2018.3 was used as the design tool. The 5G optical repeater digital transceiver unit proposed in this paper converts the 5G RF signal input to the ADC into digital and transmits it to the JIG through CPRI and outputs the downlink data signal received from the JIG through the CPRI to the DAC. And evaluated the performance. The experimental results showed that flatness, Return Loss, Channel Power, ACLR, EVM, Frequency Error, etc. exceeded the target set value.

• Korean Journal of Human Ecology
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• v.17 no.3
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• pp.399-411
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• 2008

The study purposes to survey teacher's and child's difficulties which full day classes of public kindergarten regrouped in the afternoon time are having. The subjects are 4 full day class pre-service kindergarten teachers and 8 full-day class children in G Metropolitan City and in J Province. Data were collected through in depth interviews and participatory observation. According to the results, the variables of teachers' difficulties in managing full day classes regrouped in the afternoon time are "living as an outsider without a sense of belonging", "living as a false teacher rather than a real class teacher", and "living as a teacher giving specialty and aptitude education". The variables of children's difficulties are "moving like a migratory bird", "watching the clock and the door", and "being unable to concentrate". The study is expected to be useful as one of basic findings for desirable management of kindergarten full day classes regrouped in the afternoon time.