• Journal of Institute of Control, Robotics and Systems
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• v.5 no.6
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• pp.724-733
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• 1999

An effective method of system modeling and dynamic scheduling for the back-end line of semiconductor manufacturing is proposed. The virtual factory, describing semiconductor manufacturing line, is designed in detail, and then a Petri net model simulator is developed for operation and control of the modular cells of the virtual factory. The petri net model is a colored timed Petri nets (CTPNs). The simulator will be utilized to analyze and evaluate various dynamic status and operatons of manufacturing environments. The dynamic schedulaer has a hierarchical structure with the higher for planning level and the lower for dynamic scheduling level. The genetic algorithm is applied to extract optimal conditions of the scheduling algorithm. The proposed dynamic scheduling is able to realize the semiconductor manufacturing environments for the diversity of products, the variety of orders by many customers, the flexibility of order change by changing market conditions, the complexity of manufacturing processes, and the uncertainty of manufacturing resources. The proposed method of dynamic scheduling is more effective and useful in dealing with such recent pressing requirements including on-time delivery, quick response, and flexibility.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.1117-1120
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• 2001

Chemical mechanical planarization(CMP) has emerged as the planarization technique of choice in both front-end and back-end integrated circuit manufacturing. Conventional CMP process utilize a polyurethane polishing pad and liquid chemical slurry containing abrasive particles. There have been serious problems in CMP in terms of repeatability and defects in patterned wafers. Since IBM's official announcement on Copper Dual Damascene(Cu2D) technology, the semiconductor world has been engaged in a Cu2D race. Today, even after~3years of extensive R&D work, the End-of-Line(EOL) yields are still too low to allow the transition of technology to manufacturing. One of the reasons behind this is the myriad of defects associated with Cu technology. Especially, dishing and erosion defects increase the resistance because they decrease the interconnection section area, and ultimately reduce the lifetime of the semiconductor. Methods to reduce dishing & erosion have recently been interface hardness of the pad, optimization of the pattern structure as dummy patterns. Dishing & erosion are initially generated an uneven pressure distribution in the materials. These defects are accelerated by free abrasive and chemical etching. Therefore, it is known that dishing & erosion can be reduced by minimizing the abrasive concentration. Minimizing the abrasive concentration by using Ce$O_2$ is the best solution for reducing dishing & erosion and for removal rate. This paper introduce dishing & erosion generating mechanism and a method for developing a semi-rigid abrasive pad to minimize dishing & erosion during CMP.