• 제목/요약/키워드: auto-routing system

검색결과 13건 처리시간 0.02초

선박용 배관의 Auto-Routing을 위한 설계 전문가 시스템 (Pipe Atuo-Routing with Design Knowledge-base)

  • 강상섭;명세현;한순흥
    • 한국CDE학회논문집
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    • 제2권1호
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    • pp.1-10
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    • 1997
  • Finding the optimum route of ship's pipes is complicated and time-consuming process. Experience of designers is the main tool in this process. To reduce design man-hours and human errors a design expert system shell and a geometric modeler is used to automate the design process. In this paper, a framework of the intelligent CAD system for pipe auto-routing is suggested, which consists of general-purpose expert system shell and a geometric modeler. The design expert system and the geometric modeling kernel have been integrated. The CADDS5 of Computervision is used as the overall CAD environment. The Nexpert Object of Neuron Data is used as the expert system shell. The CADDS5 ISSM is used as the interface that creates and modifies geometric models of pipes. Existing algorithms for the routing problem have been analyzed. Most of them are to solve the 2-D circuit routing problems. Ship piping system, specially within the engine room, is a complicated, large scale 3-D routing problem. Methods of expert system have been used to find the route of ship pipes on the main deck.

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최단경로를 이용한 PCB 자동 배선 시스템 설계 (The Design of PCB Automatic Routing System using the Shortest Path)

  • 우경환;이용희;임태영;이천희
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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    • pp.257-260
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    • 2001
  • Routing region modeling methods for PCB auto-routing system in Shape based type(non-grid method) used region process type and the shape located in memory as a individual element, and this element consumed small memory due to unique data size. In this paper we design PCB(Printed Circuit Board) auto-routing system using the auction algorithm method that 1) Could be reached by solving the shortest path from single original point to various destination, and 2) Shaped based type without any memory dissipation with the best speed. Also, the auto-routing system developed by Visual C++ in Window environment, and can be used in IBM Pentium computer or in various individual PC system.

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CABLE AUTO-ROUTING PROGRAM 개발

  • 배순삼;최태우;김중래;이익룡
    • 대한조선학회지
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    • 제30권1호
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    • pp.19-27
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    • 1993
  • 현재 당사에서 개발한 ROUCAS SYSTEM은 조선 전장 설계 PACKAGE에 있어 혁신적인 SYSTEM으로 부상하고 있고, 앞으로 당사 전장 설계분야에서 많은 M/H감소를 기대하고 있다. ROUCAS SYSTEM은 6개의 MODULE로 구성되어 있고, CABLE AUTO-ROUTING 은 CABLE PLAN MODULE에 속해 있으며 ROUCAS SYSTEM의 핵심이라고 할 수가 있다.

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Auction 알고리즘을 이용한 Shape Based 방식에 의한 PCB 자동 배선에 관한 연구 (A Study on the PCB automatic routing by shape based method using the auction algorithm)

  • 우경환;이천희
    • 정보처리학회논문지A
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    • 제8A권3호
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    • pp.269-278
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    • 2001
  • 자동배선 시스템의 배선영역 모델링 방법은 그리드와 논 그리드 방식을 사용하고 있다. 그리드 방식은 PCB상에 전기적, 물리적 요소들이 적다 할지라도 보드와 그리드의 크기에 제약을 받기 때문에 자동배선 속도를 감소시키는 단점을 가지고 있다. 따라서 메모리 용량을 증가 시키게 된다. 논 그리드 방식(Shape based type)은 영역처리 방식을 사용하며, 배선영역에서 그리드 방식보다 44.2% 메모리 감소효과가 있다. 따라서 Via 수는 55.5%의 감소 효곽가 있으며, 총 배선 시간도 기존 PCB시스템보다 83.3% 향상되었다. 본 논문에서는 단일 원점에서 여러 목적지에 가장 빠르게 도달 할 수 있고 최단 경로 문제를 해결하는 auction 알고리즘을 적용한 Shape based 방식에 의하여 메모리 낭비 없이 빠른 속도로 자동 배선할 수 있는 PCB 자동 배선 시스템을 개발하였다. 또한 본 시스템은 IBM Pentium 컴퓨터 Windows 환경에서 Visual C++언어로 개발하였으며 다른 PC 와도 호환성을 가질수 있도록 개발 하였다.

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The development of a practical pipe auto-routing system in a shipbuilding CAD environment using network optimization

  • Kim, Shin-Hyung;Ruy, Won-Sun;Jang, Beom Seon
    • International Journal of Naval Architecture and Ocean Engineering
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    • 제5권3호
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    • pp.468-477
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    • 2013
  • An automatic pipe routing system is proposed and implemented. Generally, the pipe routing design as a part of the shipbuilding process requires a considerable number of man hours due to the complexity which comes from physical and operational constraints and the crucial influence on outfitting construction productivity. Therefore, the automation of pipe routing design operations and processes has always been one of the most important goals for improvements in shipbuilding design. The proposed system is applied to a pipe routing design in the engine room space of a commercial ship. The effectiveness of this system is verified as a reasonable form of support for pipe routing design jobs. The automatic routing result of this system can serve as a good basis model in the initial stages of pipe routing design, allowing the designer to reduce their design lead time significantly. As a result, the design productivity overall can be improved with this automatic pipe routing system.

Q10 더미를 이용한 어린이용 안전장치 동적 성능 평가 (A Study on Child Restraints System for Q10 dummy in frontal sled test)

  • 김승기;오형준
    • 자동차안전학회지
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    • 제7권1호
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    • pp.13-19
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    • 2015
  • Recently, Child safety has become one of the issue with Q10 dummy representing large child. The objective of this paper was to evaluate performance of three child restraints system (backless booster, high-back booster and without booster) by changing D-ring location in the rear seat. Sled tests were carried out with a Q 10 in 64km/h frontal impact. Before the dynamic sled tests, we assessed dummy positioning with difference in CRS types and height adjustment positions. Dynamic sled test results indicated that there is different performance of CRS types and belt routing. These test results will use as base line data for development CRS safety performance for Q 10.

IPv6 라우터에서의 Router Advertisement 적용 방안에 관한 연구 (Study of Router Advertisement application plan in IPv6 router)

  • 신영수;양미정;강유화;김태일
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2005년도 학술대회 논문집 정보 및 제어부문
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    • pp.469-471
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    • 2005
  • Paper searches Neighbor Discovery Protocol's IPv6 address AutoConfiguration function that is IPv6's point technology. Also, I study plan to apply Router Advertisement function to Router. Router is formed whole system by Routing Process Card that do manager and Line Card that take charge of Packet Forwarding. Present plan that embody Router Advertisement function to Line Card.

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센서 네트워크 기반 이상 데이터 복원 시스템 개발 (Design of A Faulty Data Recovery System based on Sensor Network)

  • 김성호;이영삼;육의수
    • 전기학회논문지P
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    • 제56권1호
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    • pp.28-36
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    • 2007
  • Sensor networks are usually composed of tens or thousands of tiny devices with limited resources. Because of their limited resources, many researchers have studied on the energy management in the WSNs(Wireless Sensor Networks), especially taking into account communications efficiency. For effective data transmission and sensor fault detection in sensor network environment, a new remote monitoring system based on PCA(Principle Component Analysis) and AANN(Auto Associative Neural Network) is proposed. PCA and AANN have emerged as a useful tool for data compression and identification of abnormal data. Proposed system can be effectively applied to sensor network working in LEA2C(Low Energy Adaptive Connectionist Clustering) routing algorithms. To verify its applicability, some simulation studies on the data obtained from real WSNs are executed.

네트워크 기반의 소형 유비쿼터스 시스템의 개발 (Designing of Network based Tiny Ubiquitous Networked Systems)

  • 황광일;엄두섭
    • 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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    • 제13권3호
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    • pp.141-152
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    • 2007
  • 본 논문에서 우리는 ELOS(Embedded Lightweight Operating System)라 불리는 이벤트 기반의 운영체제와 멀티흡 에드혹 라우팅 프로토콜로 구성된 네트워크 기반의 소형 실시간 시스템의 구조를 제시한다. 효율적인 실시간 프로세싱을 위하여 보장된 시간 슬롯을 가진 조건적 선점형 FCFS 스케줄러가 개발되었다. 보다 정교한 네트워크 구성을 위하여 무선 에이전트 노드를 통한 반자동 구성(semi-auto configuration) 방식을 사용한다. 개발된 소프트웨어 시스템은 자체 개발한 소형 하드웨어 프로토타입에서 구현되었다. 또한, 제안된 시스템의 성능을 평가하기 위해서, 우리는 유비쿼터스 네트워크 테스트 베드를 개발했고, 다양한 환경에서의 실험이 이루어 졌다. 실험 결과를 통하여 제안된 ELOS 시스템은 실시간 제약을 가진 네트워크 기반의 소형 유비쿼터스 시스템에 상당히 알맞은 시스템이라는 것을 확인한다.

An ASIC Implementation of Fingerprint Thinning Algorithm

  • Jung, Seung-Min
    • Journal of information and communication convergence engineering
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    • 제8권6호
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    • pp.716-720
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    • 2010
  • This paper proposes an effective fingerprint identification system with hardware block for thinning stage processing of a verification algorithm based on minutiae with 39% occupation of 32-bit RISC microprocessor cycle. Each step of a fingerprint algorithm is analyzed based on FPGA and ARMulator. This paper designs an effective hardware scheme for thinning stage processing using the Verilog-HDL in $160{\times}192$ pixel array. The ZS algorithm is applied for a thinning stage. The logic is also synthesized in $0.35{\mu}m$ 4-metal CMOS process. The layout is performed based on an auto placement-routing and post-simulation is performed in logic level. The result is compared with a conventional one.