• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.3
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• pp.40-47
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• 2011

This paper addresses the problem of fault detection and tolerance for asynchronous sequential machines using state feedback control. The considered asynchronous machine is affected by intermittent faults. When intermittent faults occur, the machine undergoes unauthorized state transitions and, for a finite duration, remains at the fault state, not responding to the change of the external input. In this paper, we postulate the scheme of detecting intermittent faults and present the existence condition and design algorithm for a robust state feedback controller that overcomes the adversarial effect of intermittent faults. We also undertake a comparative study between the previous control scheme for transient faults and the present strategy for intermittent faults. The design procedure for the proposed controller is described in a case study.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.451-453
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• 2007

This paper describes the design of an asynchronous implementation of a sensor network processor. The main purpose of this work is the reduction of power consumption in sensor network node processors and the research presented here tries to explore the suitability of asynchronous circuits for this purpose. The Handshake Solutions toolkit is used to implement an asynchronous version of a sensor processor. The design is made compact, trading area and leakage power savings with dynamic power costs, targeting the typical sparse operating characteristics of sensor node processors. It is then compared with a synchronous version of the same processor. Both versions are then compared with existing commercial processors in terms of power consumption.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.4
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• pp.11-19
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• 2008

The problem of controlling asynchronous sequential machines is addressed in this paper Corrective control means to make behavior of an asynchronous sequential machine equal to that of a given model. The main objective is to develope a corrective controller, especially when a model is given as nondeterministic, or a set of reference models. We first review representation of nondeterministic models and model matching problems with nondeterministic models, which are presented in the companion paper. We then propose necessary and sufficient conditions for the existence of corrective controllers and describe their design procedure. To show the applicability, the proposed control scheme is demonstrated in an example.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.253-261
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• 2013

In this paper, we study the problem of controlling composite asynchronous sequential machines. The considered asynchronous machine consists of two input/state machines in cascade connection, where the output of the front machine is delivered to the input channel of the rear machine. The objective is to design a corrective controller realizing model matching such that the stable state behavior of the closed-loop system matches that of a reference model. Since the controller receives the state feedback of the rear machine only, there exists uncertainty about the present state of the front machine. We specify the existence condition for a corrective controller given the uncertainty. The design procedure for the proposed controller is described in a case study.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.145-148
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• 2000

A 16bit asynchronous multiplier has been designed using micropipelind structure with 2 phase and data bundling. And 4-radix modified Booth algorithm, CPlatch(Cature-Pass latch) and modified 4-2 counters have adopted in this design. It is implemented in 0.65$\mu\textrm{m}$ double-poly/double-metal CMOS technology by using 12,074 transistors with core size of 1.4${\times}$1.8$\textrm{mm}^2$. And our design results in a computation rate 55MHz a supply voltage of 3.3V.

• Proceedings of the IEEK Conference
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• 2000.06a
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• pp.61-64
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• 2000

In this paper, we design up-down converter for asynchronous IMT-2000 base station using W-CDMA(Wideband Code Division Multiple Access) technology. This up-down converter(UDC) has AGC (Automatic Gain Control), TPTL(Transmitting Power Tracing Loop), RSSI(Received Signal Strength Indicator) function. And for the cell control of BS(Base Station), breathing, blossoming, wilting function also available. This UDC has diversity structure for better performance.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.349-352
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• 2001

As microprocessor and SOC (System On a Chip) performance moves into the GHz speed, the high-speed asynchronous design is becoming challenge due to the disadvantageous power and speed aspects in synchronous designs. The next generation on-chip systems will consist of multiple independently synchronous modules and asynchronous modules for higher performance, so the interface module for data transfer between multiple clocked IPs is designed with Xilinx FPGA and simulated with RISC microprocessor.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.733-736
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• 1999

In this Paper, Bit selectable and Bi-directional Interface Port is described, which can communicate data with the peripheral devices. Specially A description of the asynchronous design method is given to remove the clock skew phenomenon and the output asynchronous control method which finds the optimal clock and controls all the enable signal of the output pins at the same time is presented. Using this technique interface ports have delay time of less-than 0.5㎱.

• International Journal of Contents
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• v.5 no.2
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• pp.53-58
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• 2009

This paper presents a novel approach in the design of a CAM for an asynchronous cache. The architecture of cache mainly consists of four units: control logics, content addressable memory, completion signal logic units and instruction memory. The pseudo-DCVSL is useful to make a completion signal which is a reference for handshake control. The proposed CAM is a very simple extension of the basic circuitry that makes a completion signal based on DI model. The cache has 2.75KB CAM for 8KB instruction memory. We designed and simulated the proposed asynchronous cache including CAM. The results show that the cache hit ratio is up to 95% based on pseudo-LRU replacement policy.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.353-356
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• 2002

Due to the increased complexity and size of digital system and the need of the H/W-S/W co-design, C/C++ based system design methodology gains more Interests than ever in EDA field. This paper suggests the methodology in which handshake module corresponding to each basic statement of C is provided of the form of STG(Signal Transition Graph) and then, C statements is synthesized into asynchronous circuit through syntax-oriented translation. The 4-phase handshaking protocol is used for the communications between modules, and the modules are synthesized by the Petrify which is asynchronous logic synthesis CAD tool.