• 한국신재생에너지학회:학술대회논문집
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• 2009.11a
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• pp.439-442
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• 2009

As a result of increasing environmental concern, the penetration of renewable power on power systems is now increasing. Wind energy can be considered as the most economical energy sources to generate electricity without depletion of fossil fuel. The penetration of wind energy from wind farm is getting larger and larger, so we need adequate control strategies for wind farm. To devise adequate control strategies for wind farm, time domain simulation analysis needs to be performed. This presents a Simultaneous Implicit-based time domain simulation algorithm for wind farm with DFAG (Doubly Fed Asynchronous generator) connected to the external power systems. This paper shows an illustrative example with a 5-bus test system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.165-175
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• 2010

This paper presents a fine-grain supply-voltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltage-control scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 nm CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.512-517
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• 1998

In a matrix converter, input side and output side are coupled with each other through switching elements. Since disturbances on either side affect directly on the other side, it requires a high-speed on-line control system to compensate them. We proposed in previous papers a new control strategy and an on-line control circuit for a matrix converter. The control circuit could keep the output voltage at commanded value against fluctuation in the supply voltage. Furthermore wave forms of the output voltage and the input current were always kept sinusoidal. The switching pattern was generated by comparing modified voltage references with a carrier. The carrier was synchronized with the supply voltage using a PLL system, which made the control circuit complicated and costly. This paper discusses on the possibility of an asynchronized carrier. Experiment results show the input current distortion in case of asynchronous carrier is bigger than that of synchronous carrier. However, the deterioration can be minimized by increased carrier frequency.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.6
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• pp.496-503
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• 2017

This study proposes a high-performance current control algorithm for a diode-bridge-type single-phase boost power factor correction (PFC) converter. The conventional asynchronous single-phase current controllers that directly control AC-type current tend to be accompanied by steady-state errors due to their poor dynamic characteristics for the transient-state, which can be attributed to bandwidth limitations and phase delays. In the proposed algorithm, an ideal current control with minimal phase delays and steady-state errors can be achieved by using a virtual DQ synchronous reference frame and by controlling the synchronous reference frame excluding the frequency component in the single-phase system. The performance of the conventional asynchronous single-phase current controller is compared with that of the proposed algorithm through simulation and experiments, and the results have confirmed the superiority of the latter.

• Journal of Institute of Control, Robotics and Systems
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• v.7 no.1
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• pp.1196-1204
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• 2001

In this paper, a new architecture of operating software associated with the component-based method is proposed. The proposed architecture comprises 문 execution module and a decision-making module. In order to make effective development and maintenance, the execution module is divided into three components. The components are referred to as Symbol, Gateway, and Control, respectively: The symbol component is for the GUI environments and the standard interfaces; the gateway component is for the network communication and the structure of asynchronous processes; the control component is for the asynchronous processing and machine setting or operations. In order to verify the proposed architecture, and off-line version of operating software is made, and its steps are as follows; I) Make virtual execution modules for the manufacturing devices such as dual-arm robot, handling robot, CNC, and sensor; ii) Make decision-making module; iii) Integrate the modules and GUI using a well-known development tools such as Microsofts Visual Basic; iv) Execute the overall operating software to validate the proposed architecture. The proposed software architecture in this paper has the advantages such as independent development of each module, easy development of network communication, and distributed processing of resources, and so on.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.6
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• pp.478-485
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• 2000

A discrete event systems (DES) is a physical system that is discrete in time and state space, asynchronous (event rather than clock-driven), and in some sense generative(or nondeterministic). This paper presents the design of fifteen modular supervisors to control an experimental CIM testbed. These supervisors are nonblocking, controllable and nonconflicting. After verification of the supervisors by simulation, the supervisors for AGV system have been implemented to demonstrate their efficacy.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.8
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• pp.1-8
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• 2010

This paper models a symbol timing offset (STO) with respect to the guard period and the maximum access delay time for asynchronous multicarrier code division multiple access (MC-CDMA) uplink systems over frequency-selective multipath fading channels. Analytical derivation shows that STO causes desired signal power degradation and generates self-interferences. This effect of the STO on the average bit error rate (BER) and the effective signal-to-noise ratio (SNR) is evaluated. The approximated BER and the SNR loss caused by STO are then obtained as closed-form expressions. The tightness between the analytical result and the simulated one is verified for the different STOs and SNRs. Furthermore, the derived analytical results are verified via Monte Carlo simulations.

• Journal of the Korean Institute of Intelligent Systems
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• v.26 no.2
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• pp.135-140
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• 2016

Corrective controllers enable fault diagnosis and tolerance for various faults in asynchronous sequential circuits without resort to redesign. In this paper, we propose a static corrective controller in order to decrease the size of the controller. Compared with dynamic controllers, static controllers can be made using only combinational circuits, as they need no inner states. We address the existence condition and design procedures for static corrective controllers that overcome state transition faults. To show the validity and advantage, the proposed controller is applied to an SEU error counter implemented on FPGA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.23-29
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• 2004

In this paper, the asynchronous quasi dual-port SRAM employing a single port structure in SRAM embedded SOC (System On Chip) is proposed. External host can access the internal SRAM freely and the data on internal SRAM can be transferred to an another external circuitry without a synchronous signal of an external host, which operates as an asynchronous dual-port SRRAH The performances of the proposed circuits and control structure are verified through the simulation and we fabricated it using a 0.35um CMOS technology. As the results, the chip shows reduced area about 20% and saved power also 20% than conventional architectures.

• 제어로봇시스템학회:학술대회논문집
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• 1986.10a
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• pp.158-163
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• 1986

This article surveys techniques and issues related to real time process control system developed for industrial control applications. It covers the system architecture and software engineering issues such as the design of data structures, scheduling of asynchronous task activities, management of shared resources, handling of interrupt and implementing an user friendly man-machine interface. Also problems associated with implementing a real-time system that supports dynamic configuration of data base is addressed.