• Proceedings of the Korean Society for Cognitive Science Conference
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• 2010.05a
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• pp.55-59
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• 2010

To examine iterocular interactions in normal subjects, we recorded EEG activity from channel O1 and O2 on 14 healthy subjects while checkerboard pattern reversals were presented to each eye with different interstimulus intervals (ISIs) ranging from 0 to 218 ms. When pattern reversals were presented asynchronously to each eye, P-1 activity evoked by each reversal was significantly suppressed compared to the activation evoked by synchronous reversals. Furthermore, when there was time delay between pattern reversals to each eye, theta (4-10 Hz) band power was also significantly decreased, whereas beta (10-30 Hz) band power was relatively preserved. Our results suggest that neural activity evoked by sustained but not yet reversed checkerboard from one eye might inhibit upcoming neural response evoked by reversed checkerboard from the other eye. Decreased P-1 activity might reflect such inhibitory interaction between two eyes. Also, decreased theta and preserved beta band power might reflect engagement of different neural circuit for binocular / monocular vision.

• Journal of the Optical Society of Korea
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• v.20 no.3
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• pp.335-342
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• 2016

We demonstrate an optical asynchronous transfer mode/wavelength division multiplexing (OATM/WDM) optical access network, using a router based on an optical header decoder to conduct next-generation communications. The router consists of a decoder or hardware analysis processing of the header bit and switches. The router in the OATM/WDM optical access network is a key technology by which to satisfy subscribers’ requests, including reliability, cost efficiency, high speed, large-capacity transmission, and elevated information security. In this study, we carry out experiments in which a header decoder delivers to 16 and 32 subscribers with a single wavelength in the router. These experiments confirm the decoder’s successful operation via hardware using 4 and 5 header bits. We propose that this system may significantly contribute toward the realization of an optical access network that provides high-quality service to subscribers of next-generation communications.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.481-482
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• 2007

This paper describes the design of a l0-bit 100 KSample/S CMOS A/D Converter for biomedical applications such as pulse oximetry, body weight scale, ECG etc. We adopted an asynchronous architecture in the 10-b DAC design and hence reduces the number of switches by 11 and resistors by 64 compared with the conventional l0-b DAC. We also reduced the power consumption compare with the conventional architecture by 0.4mW. Output offset cancellation technique is applied to the design of comparator. The total power consumption of designed circuit is 190uW at the supply voltage of 1.8V with the 0.18um general CMOS technology.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.24 no.62
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• pp.11-20
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• 2001

At the initial deployment of B-ISDN, the heterogeneity of services and the bandwidth requirement make dimensioning of B-ISDN much more complicated than the dimensioning of homogeneous circuit or packet switched networks. Therefore B-ISDN must be extended gradually according to future telecommunication technology or service demands. In this paper, we propose a mathematical formulation for dimensioning problem of B-ISDN extension, considering the characteristics of ATM(Asynchronous Transfer Mode) such as various quality of services, the statistical multiplexing effects of VPCs(Virtual Path Connections) and the modularity of transmission links allocated when new B-ISDN nodes are given. The algorithm based on the simultaneous linear approximation technique and Lagrangian relaxation method and some numerical results are also presented.

• Journal of Semiconductor Engineering
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• v.2 no.1
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• pp.99-108
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• 2021

Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC) seem to become the hottest ADC architecture during the past decade in implementing energy-efficient high performance ADCs. In this overview, we will review what kind of circuit techniques and architectural advances have contributed to place the SAR ADC architecture at its current position, beginning from a single SAR ADC and moving to various hybrid architectures. At the end of this overview, a recently reported compact and high-speed SAR-Flash ADC is introduced as one design example of SAR-based hybrid ADC architecture.

• Journal of Advanced Marine Engineering and Technology
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• v.35 no.6
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• pp.842-848
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• 2011

A fabricated hybrid control board using multi-communication is designed with a low power 8-bit microcontroller, ATxmega128A1. The microcontroller consists of 8 UART (Universal asynchronous receiver/transmitter) ports, 2 kbytes EEPROM, 128 kbytes flash memory, 8 kbytes SRAM. The 8 URAT ports are used for a multi-communication modem, a GPS module, etc. The EEPROM is used for saving a configuration for running programs, and the flash memory of 128 kbytes is used for storing a F/W (Firm Ware), and the 8 kbytes SRAM is used for stack and for storing memory of global variables while running programs. If we use the multi-communication of CDMA, TRS and RF to remotely control Aid to Navigation, it is able to remove the communication shadow area. Even though there is a shadow area for an individual communication method, we can select an optimal communication method. The compatibility of data has been enhanced as using of same data frame per communication device. For the test, 8640 of data have been collected from each buoy during 30 days in every 5 minutes and the receiving rate of the data has shown more than 85 %.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.3
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• pp.577-582
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• 2016

The synchronous TDC(Time-to-Digital Converter) of counter-type using current-conveyor is designed by $0.18{\mu}m$ CMOS process and the supply voltage is 3 volts. In order to compensate the disadvantage of a asynchronous TDC the clock is generated when the start signal is applied and the clock is synchronized with the start signal. In the asynchronous TDC the error range of digital output is from $-T_{CK}$ to $T_{CK}$. But the error range of digital output is from 0 to $T_{CK}$ in the synchronous TDC. The error range of output is reduced by the synchronization between the start signal and the clock when the timing-interval signal is converted to digital value. Also the structure of the synchronous TDC is simple because there is no the high frequency external clock. The operation of designed TDC is confirmed by the HSPICE simulation.

• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.7-13
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.6
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• pp.698-706
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• 2016

Orthogonal frequency division multiplexing (OFDM) has high peak to power ratio (PAPR). High PAPR makes problems such as signal distortion and circuit cost increasing. To solve the problemsm several PAPR reduction methods have been proposed. However, synchronization and orthogonality in OFDM systems may be a limitation to reduce latency for 5G networks. Generalized frequency division multiplexing (GFDM) is one of the possible solutions for asynchronous and non-orthogonal systems, which are more preferable to reduce the latency. However, multiple subsymbols in GFDM result in more superposition in time domain, GFDM has higher PAPR. Selective mapping (SLM) is one of PAPR reduction techniques in OFDM, which uses phase shift. The PAPR of GFDM SLM is compared to conventional GFDM and OFDM SLM in terms of PAPR reduction enhancement via numerical simulations. In addition, the out-of-band performance is analyzed in the aspect of asynchronous condition interference.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.671-674
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• 2009

We design a low-power and low-area asynchronous EEPROM of 256 bits used in a passive UHF RFID tag chip. For a low-power solution, we use a supply voltage of 1.8V and design a Dickson charge pump using N-type Schottky diodes with a low-voltage characteristic. And we use an asynchronous interface and a separate I/O method for a low-area solution of the peripheral circuit of the designed EEPROM. And we design a Dickson charge pump using N-type Schottky diodes to reduce an area of DC-DC converter. The layout area of the designed EEPROM of 256 bits with an array of 16 rows and 16 columns using $0.18{\mu}m$ EEPROM process is $311.66{\times}490.59{\mu}m^2$.