• Transactions of the Korean Society of Mechanical Engineers A
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• v.20 no.1
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• pp.35-43
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• 1996

A computer program for automatic deriving the symbolic equations of motion for robots using the programming language MATHEMATICA has been developed. The program, developed based on the Lagrange formalism, is applicable to the closed chain robots as well as the open chain robots. The closed chains are virtually cut open, and the kinematics and dynamics of the virtual open chain robot are analyzed. The constraints are applied to the virtually cut joints. As a result, the spatial closed chain robot can be considered as a tree structured open chain robot with kinematic constraints. The topology of tree structured open chain robot is described by a FATHER array. The FATHER array of a link indicates the link that is connected in the direction of base link. The constraints are represented by Lagrange multipliers. The parallel robot, DELTA, having three-dimensional closed chains is modeled and simulated to illustrate the approach.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.9
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• pp.1055-1063
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• 1999

공개키 암호화 시스템에서 주된 연산은 512비트 이상의 큰 수에 의한 모듈러 지수 연산으로 표현되며, 이 연산은 내부적으로 모듈러 곱셈을 반복적으로 수행함으로써 계산된다. 본 논문에서는 Montgomery 알고리즘을 분석하여 right-to-left 방식의 모듈러 지수 연산에서 공통으로 계산 가능한 부분을 이용하여 모듈러 제곱과 모듈러 곱셈을 동시에 수행하는 선형 시스톨릭 어레이를 설계한다. 설계된 시스톨릭 어레이는 VLSI 칩과 같은 하드웨어로 구현함으로써 IC 카드나 smart 카드에 이용될 수 있다.Abstract The main operation of the public-key cryptographic system is represented the modular exponentiation containing 512 or more bits and computed by performing the repetitive modular multiplications. In this paper, we analyze Montgomery algorithm and design the linear systolic array for performing modular multiplication and modular squaring simultaneously using the computable part in common in right-to-left modular exponentiation. The systolic array presented in this paper could be designed on VLSI hardware and used in IC and smart card.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.1C
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• pp.140-148
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• 2008

Using the self duality of an optimal normal basis(ONB) of type II, we present a bit parallel and bit serial systolic arrays over GF($2^m$) which has a low hardware complexity and a low latency. We show that our multiplier has a latency m+1 and the basic cell of our circuit design needs 5 latches(flip-flops). Comparing with other arrays of the same kinds, we find that our array has significantly reduced latency and hardware complexity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.94-104
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• 2008

In this paper, we propose a new architecture of multiplier-and-accumulator (MAC) for high speed multiplication and accumulation arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator which has the largest delay in MAC was removed and its function was included into CSA, the overall performance becomes to be elevated. The proposed CSA tree uses 1's complement-based radix-2 modified booth algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of operands. The CSA propagates the carries by the least significant bits of the partial products and generates the least significant bits in advance for decreasing the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits not the output of the final adder for improving the performance by optimizing the efficiency of pipeline scheme. The proposed architecture was synthesized with $250{\mu}m,\;180{\mu}m,\;130{\mu}m$ and 90nm standard CMOS library after designing it. We analyzed the results such as hardware resource, delay, and pipeline which are based on the theoretical and experimental estimation. We used Sakurai's alpha power low for the delay modeling. The proposed MAC has the superior properties to the standard design in many ways and its performance is twice as much than the previous research in the similar clock frequency.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.40 no.3
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• pp.181-189
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• 2016

An analytical model was developed by Sim to estimate the two-phase damping ratio for upward two-phase flow perpendicular to horizontal tube bundles. The parameters of two-phase flow, such as void fraction and pressure loss evaluated in the model, were calculated based on existing experimental formulations. However, it is necessary to implement a few improvements in the formulations for the case of tube bundles. For the purpose of the improved formulation, we need more information about the two-phase parameters, which can be found through experimental test. An experiment is performed with a typical normal square array of cylinders subjected to the two-phase flow of air-water in the tube bundles, to calculate the two-phase Euler number and the two-phase friction multiplier. The pitch-to-diameter ratio is 1.35 and the diameter of cylinder is 18mm. Pressure loss along the flow direction in the tube bundles is measured with a pressure transducer and data acquisition system to calculate the two-phase Euler number and the two-phase friction multiplier. The void fraction model by Feenstra et al. is used to estimate the void fraction of the two-phase flow in tube bundles. The experimental results of the two phase friction multiplier and two-phase Euler number for homogeneous and non-homogeneous two-phase flows are compared and evaluated against the analytical results given by Sim's model.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.115-122
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• 2004

In this paper, the multiple-valued adders and multipliers are implemented by current-mode CMOS. First, we implement the 3-valued T-gate and the 4-valued T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second we implement the circuits to be realized 2-variable 3-valued addition table and multiplication table over finite fields $GF(3^2)$, and 2-variable 4-valued addition table and multiplication table over finite fields $GF(4^2)$ with the multiple-valued T-gates. Finally, these operation circuits are simulated under $1.5\mutextrm{m}$ CMOS standard technology, $15\mutextrm{A}$ unit current, and 3.3V VDD voltage Spice. The simulation results have shown the satisfying current characteristics. The 3-valued adder and multiplier, and the 4-valued adder and multiplier implemented by current-mode CMOS is simple and regular for wire routing and possesses the property of modularity with cell array. Also, since it is expansible for the addition and multiplication of two polynomials in the finite field with very large m, it is suitable for VLSI implementation.

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.3
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• pp.99-105
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• 2009

This paper suggests novel signal processing methods for optimal beamforming of smart antenna system in CDMA2000 mobile communication environments. This method utilize characteristics of the reverse pilot channel of CDMA2000 mobile communication systems, and applies them to improve the performance of an adaptive algorithm, which is used to a smart antenna system for beamforming. To perform the best beamforming, it is important to get an exact beamforming algorithm. This paper proposed an algorithm based on Laglange multiplier which has such an adaptive process, and also proposed the method to demodulate the received signal through array antenna using pilot channel in CDMA2000 environment. This paper analysed the enhanced performance of proposed algorithm in various signal environment through signal modeling of physical layer in CDMA2000 reverse link.

• Journal of Korea Society of Industrial Information Systems
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• v.7 no.3
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• pp.1-8
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• 2002

Modular Multiplication in Galois Field GF(2/sup m/) is a basic operation for many applications, particularly for public key cryptography. This paper presents a new architecture that can process modular multiplication on GF(2/sup m/) per m clock cycles using a cellular automata. Proposed architecture is more efficient in terms of the space and time than that of systolic array. Furthermore it can be efficiently used for the hardware design for exponentiation computation.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1573-1576
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• 1987

A 4-bit parallel-series A/D converter has been designed using a new matrix circuit and breadboarded with transister array(TPQ2483). The simple matrix circuit is substituted for D/A converter and sebtracter-multiplier. The system has been simulated with SPICE. This converter is capable of operating at clock rate of 20MHz.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.376-379
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• 1999

The wavelet transform chip is implemented with Daubechies' 4 tap filter. It works at 20MHz in Field Programmable Gate array (FPGA) implementation of Quadrature Mirror Filter(QMF) Lattice Structure. In this paper, the structure contains taro-channel quadrature mirror filter, data format converter(DFC), delay control unit(DCU), and three 20$\times$8 bits real multiplier. The structures for the DFC and DCU need to he regular and scalable, require minimum number of regular, and thereby lead to an efficient and scalable architecture for the Discrete Wavelet Transform(DWT). These results present the possibility that it can be used in Digital Signal Processing(DSP) application faster than Fourier transform at small area with lour cost.