• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.58-70
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• 1990

This paper describes a VLSI implementation of real-time two dimensional DCT processor for the subprimary rate video codec system. The proposed architecture exploits the parallelism and concurrency of the distributes architecture for vector inner product operation of DCT and meets the CCITT performance requirements of video codec for full CSIF 30 frames/sec. It is also shown that this architecture satisfies all the CCITT IDCT accuracy specification by simulating the suggested architecture in bit level. The efficient VLSI disign methodology to design suggested architecture is considered and the module generator oriented design environments are constructed based on SUN 3/150C workstation. Using the constructed design environments. the suggensted architecture have been designed by double metal 2micron CMOS technology. The chip area fo designed 8x8 2-D DA-DCT (Distributed Arithmetic DCT) processor is about 3.9mmx4.8mm.

• Spatial Information Research
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• v.17 no.3
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• pp.371-379
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• 2009

Recently, GPU (Graphics Processing Unit) has been improved rapidly on the need of speed for gaming. As a result, GPU contains multiple ALU (Arithmetic Logic Unit) for parallel processing of a lot of graphics data, such as transform, ray tracing, etc. Therefore, this paper proposed a technique for parallel processing of spatial data using GPU. Spatial data consists of multiple coordinates, and each coordinate contains value of x and y axis. To display spatial data graphics operations have to be processed to large amount of coordinates. Because the graphics operation is identical and coordinates are multiple data, SIMD (Single Instruction Multiple Data) parallel processing of GPU can be used for processing of spatial data to improve performance. This paper implemented SIMD parallel processing of spatial data using two kinds of SDK (Software Development Kit). CUDA and ATI Stream are used for NVIDIA and ATI GPU respectively. Experiments that measure time of calculation for graphics operations are carried out to observe enhancement of performance. Experimental result is reported that proposed method can enhance performance up to 1,162% for graphics operations. The proposed method that uses parallel processing with GPU for spatial data can be generally used to enhance performance for applications which deal with large amount of spatial data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.75-84
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• 2004

In this paper, we proposed an efficient hardware architecture of line-based lifting algorithm for Motion JPEG2000. We proposed a new architecture of a lifting-based filtering cell which has an optimized and simplified structure. It was implemented in a hardware accommodating both (9,7) and (5,4) filter. Since the output rate is linearly proportional to the input rate, one can obtain the high throughput through parallel operation simply by adding the hardware units. It was implemented into both of ASIC and FPGA The 0.35${\mu}{\textrm}{m}$ CMOS library from Samsung was used for ASIC and Altera was the target for FRGA. In ASIC, the proposed architecture used 41,592 gates for the lifting arithmetic and 128 Kbit memory. For FPGA it used 6,520 LEs(Logic Elements) and 128 ESBs(Embedded System Blocks). The implementations were stably operated in the clock frequency of 128MHz and 52MHz, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11C
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• pp.1491-1497
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• 2004

The psychoacoustic model in MPEG audio layer-III (MP3) encoder is optimized for the fixed-point processing. The optimization process consists of determining the data word length of arithmetic unit and the algorithm for transcendental functions that are often used in the psychoacoustic model. In order to determine the data word length, we defined a statistical model expressing the relation between the fixed-point operation errors of the psychoacoustic model and the probability of alteration of the allocated bits doe to these errors. Based on the simulations using this model, we chose a 24-bit data path and constructed a 24-bit fixed-point MP3 encoder. Sound quality tests using the constructed fixed-point encoder showed a mean degradation of -0.2 on ITU-R 5-point audio impairment scale.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.12A
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• pp.1009-1018
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• 2003

A new fading channel estimation technique is proposed for an OFDM based modem In the ITS system. The algorithm is based on the transfer function extraction of the channel using the pilot signals and compensated the channel preceding the equalization. The newly derived algorithm is division-free arithmetic operations allows the faster circuit operation and the smaller circuit size. Proposed techniques compensate firstly the distortion which is generated at fading channels and secondly eliminate inter-symbol interference. All algorithms are suitability estimated and improved for a system implementation using digital circuits. As the results, the circuit size is reduced by 20% of the conventional design and achieved about 10% performance improvement at low SNR under 10dB in case of ITS system adapted 16-QAM mode.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.4
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• pp.143-150
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• 2013

The School Curriculum amend in 2007 mandates the contents from which students can learn the principles and concepts of computer science. Computer Science is one of the most rapidly changing subjects, and the Informatics textbook should accurately explain the basic principles and concepts based on the latest technology. However, we found that the middle school textbooks in circulation lack accuracy and consistency in describing CPU. This paper attempted to discover the root-cause of the fallacy and suggest timely and appropriate explanation based on the historical and technical analysis. According to our study, it is appropriate to state that CPU is composed of datapath and control unit. The Datapath performs operations on data and holds data temporarily, and it is composed of the hardware components such as memory, register, ALU and adder. The Control unit decides the operation types of datapath elements, main memory and I/O devices. Nevertheless, considering the technological literacy of middle school students, we suggest the terms, 'arithmetic part' and 'control part' instead of datapath and control unit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2031-2038
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• 2008

A small-area and high-speed authentication/security processor (WUSB_Sec) IP is designed, which performs the 4-way handshake protocol for authentication between host and device, and data encryption/decryption of wireless USB system. The PRF-256 and PRF-64 are implemented by CCM (Counter mode with CBC-MAC) operation, and the CCM is designed with two AES (Advanced Encryption Standard) encryption coles working concurrently for parallel processing of CBC mode and CTR mode operations. The AES core that is an essential block of the WUSB_Sec processor is designed by applying composite field arithmetic on AF$(((2^2)^2)^2)$. Also, S-Box sharing between SubByte block and key scheduler block reduces the gate count by 10%. The designed WUSB_Sec processor has 25,000 gates and the estimated throughput rate is about 480Mbps at 120MHz clock frequency.

• Korean Journal of Acupuncture
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• v.36 no.1
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• pp.44-51
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• 2019

Objectives : Teaching the standardized acupuncture point locations and improving the accuracy of acupoint locations through objective evaluation is a very important part of Korean medicine education. The aim of this study is to develop a dummy system for evaluation and support of teaching acupoint location in meridian and acupoints classes and to introduce the developed system. Methods : We established a protocol for the development of the system. The protocol included definition of usage purpose, definition of its essential performance, and set of scope. The system compares the amount of light at the target acupoint with the amount of light at the other sites to determine whether the target acupoint is properly specificated. Results : A prototype of the system was built according to the protocol and consists of light emitter, dummy, control/operation, input part and output part. The light emitter projects laser beam passing through the skin of the dummy. Light sensors were attached inside the acupoints of the dummy. Three types of light sensors were selected depending on the location of the acupoints. The arithmetic, input, and output parts were constructed using Arduino and Raspberry pi boards. The developed system was applied in class. Conclusions : It is thought that the dummy system for evaluation and support of teaching acupoint location can be used as a training model in order to help teach standardized acupoint locations and objective evaluation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.3
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• pp.41-48
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• 2004

Finite field multiplication and division are important arithmetic operation in error-correcting codes and cryptosystems. The elements of the finite field GF($2^m$) are represented by bases with a primitive polynomial of degree m over GF(2). We can be easily realized for multiplication or computing multiplicative inverse in GF($2^m$) based on a normal basis representation. The number of product terms of logic function determines a complexity of the Messay-Omura multiplier. A normal basis exists for every finite field. It is not easy to find the optimal normal element for a given primitive polynomial. In this paper, the generating method of normal basis is investigated. The normal bases whose product terms are less than other bases for multiplication in GF($2^m$) are found. For each primitive polynomial, a list of normal elements and number of product terms are presented.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.2
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• pp.49-61
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• 2009

Finite Field multiplication operation is one of the most important operations in the finite field arithmetic. Recently, Fan and Dai introduced a Shifted Polynomial Basis(SPB) and construct a non-pipeline bit-parallel multiplier for $F_{2^n}$. In this paper, we propose a new bit-parallel shifted polynomial basis type I and type II multipliers for $F_{2^n}$ defined by an irreducible trinomial $x^{n}+x^{k}+1$. The proposed type I multiplier has more efficient the space and time complexity than the previous ones. And, proposed type II multiplier have a smaller space complexity than all previously SPB multiplier(include our type I multiplier). However, the time complexity of proposed type II is increased by 1 XOR time-delay in the worst case.