• Journal of Information Processing Systems
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• v.18 no.1
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• pp.97-114
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• 2022

Interest is increasing in electrocardiogram (ECG) signal analysis for embedded devices, creating the need to develop an algorithm suitable for a low-power, low-memory embedded device. Linear approximation of the ECG signal facilitates the detection of fiducial points by expressing the signal as a small number of vertices. However, dynamic programming, a global optimization method used for linear approximation, has the disadvantage of high complexity using memoization. In this paper, the calculation area and memory usage are improved using a linear approximated template. The proposed algorithm reduces the calculation area required for dynamic programming through local optimization around the vertices of the template. In addition, it minimizes the storage space required by expressing the time information using the error from the vertices of the template, which is more compact than the time difference between vertices. When the length of the signal is L, the number of vertices is N, and the margin tolerance is M, the spatial complexity improves from O(NL) to O(NM). In our experiment, the linear approximation processing time was 12.45 times faster, from 18.18 ms to 1.46 ms on average, for each beat. The quality distribution of the percentage root mean square difference confirms that the proposed algorithm is a stable approximation.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1474-1479
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• 2004

In this paper, the design of the network system using the CAN and the analysis of effects of time delay in the system are presented. A conventional implementation technique induces many problems because of the amount and complexity of wiring and maintenance problems. The network system reduces these problems, but it cause another problem; time delay. Time delay in a sampling time does not have much effects on the system, but time delay over the sampling time changes the control frequency and ended up makes the system unstable. It is verified that time delay between each parts has different effects on the entire system. The results from this paper will be a base for studying algorithms to reduce effects of time delay in the system using the CAN.

• Journal of the Korean Society for Aviation and Aeronautics
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• v.22 no.2
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• pp.1-8
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• 2014

This paper introduces a new framework of predicting the arrival time of an aircraft by incorporating the probabilistic information of what type of trajectory pattern will be applied by human air traffic controllers. The proposed method is based on identifying the major patterns of vectored trajectories and finding the statistical relationship of those patterns with various traffic complexity factors. The proposed method is applied to the traffic scenarios in real operations to demonstrate its performances.

• Journal of Korea Game Society
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• v.14 no.2
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• pp.77-84
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• 2014

Presence of soft shadow effects from an area light makes virtual scenes look more realistic. However, since computation of soft shadow effects takes a long time, acceleration methods are required to apply it to real-time 3D applications. Many researches assumed that area lights are white rectangles. We suggest a new method which renders soft shadows under the area light source having arbitrary shape and color. In order to approximate visibility test, we use a shadow mapping result near a pixel. Complexity of shadow near a pixel is used to determine degree of precision of our visibility estimation. Finally, our method can present more realistic soft shadows for the area light that have more general shape and color in real-time.

• Journal of Digital Convergence
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• v.15 no.8
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• pp.127-135
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• 2017

Consumers tend to feel concern about disclosure of personal information and, at the same time, to avoid inconvenience of procedural complexity caused by the privacy protections. The purpose of current paper is to investigate relationships between opt-in procedural complexity and shopping behavior using smart phones, moderating by the amount of visual attentions using eyetrackers. Therefore, we created a virtual mobile Web-site in which the complexity of opt-in procedures in our experiment is manipulated and measured. Also, we measured the dwell-time of area of interest using SMI-RED 250 instrument for tracking the real eye movement. Results indicated that the levels of procedural complexity are related to repurchase, indicating a moderating effect of the amount of visual attentions. Finally, we discussed several theoretical and practical implications of management for mobile commerce.

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.37-43
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• 2020

In this paper, we propose an efficient AB² multiplication algorithm using SPB(shifted polynomial basis) over finite fields. Using the feature of the SPB, we split the equation for AB² multiplication into two parts. The two partitioned equations are executable at the same time, and we derive an algorithm that processes them in parallel. Then we propose an efficient semi-systolic AB² multiplier based on the proposed algorithm. The proposed multiplier has less area-time (AT) complexity than related multipliers. In detail, the proposed AB² multiplier saves about 94%, 87%, 86% and 83% of the AT complexity of the multipliers of Wei, Wang-Guo, Kim-Lee, Choi-Lee, respectively. Therefore, the proposed multiplier is suitable for VLSI implementation and can be easily adopted as the basic building block for various applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4C
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• pp.337-342
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• 2010

In this paper, a new architecture for digit-parallel/bit-serial GF($2^m$) multiplier with low complexity is proposed. The proposed multiplier operates in polynomial basis of GF($2^m$) and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the digit-parallel/bit-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But the traditional digit-parallel/bit-serial multiplier needs extra hardware for high speed. In this paper a new low complexity efficient digit-parallel/bit-serial multiplier is presented.

• Journal of Korea Society of Industrial Information Systems
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• v.7 no.5
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• pp.167-174
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• 2002

This paper analyzes the characteristics of three multipliers and squarers in finite fields GF(2/sup m/) from the point of view of processing time and area complexity. First, we analyze structures of three multipliers and squarers: 1) Systolic array structure, 2), LFSR structure, and 3) CA structure. To make performance analysis, each multiplier and squarer was modeled in VHDL and was synthesized for FPGA implementation. The simulation results show that CA structure is the best from the point view of processing time, and LFSR structure is the best from the point of view of area complexity.

• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.616-619
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• 2007

Nowadays, urbanized area expands its boundary, and distribution of urbanized area is gradually transformed into more complicated pattern. In Korea, SMA(Seoul Metropolitan Area) has outstanding urbanized area since 1950s. But it is ambiguous whether urban distribution is clustered or dispersed. This study aims to show the way in which expansion of urbanized area impacts on spatial distribution pattern of urbanized area. We use quadrat analysis, nearest-neighbor analysis and fractal analysis to know distribution pattern of urbanized area in time-series urban growth. The quadrat analysis indicates that distribution pattern of urbanized area is clustered but the cohesion is gradually weakened. And the nearest-neighbor analysis shows that point patterns are changed that urbanized area distribution pattern is progressively changed from clustered pattern into dispersed pattern. The fractal dimension analysis shows that 1972's distribution dimension is 1.428 and 2000's dimension is 1.777. Therefore, as time goes by, the complexity of urbanized area is more increased through the years. As a result, we can show that the cohesion of the urbanized area is weakened and complicated.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.453-464
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• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.