• Title/Summary/Keyword: area-time complexity

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Optimizing Work-In-Process Parameter using Genetic Algorithm (유전 알고리즘을 이용한 Work-In-Process 수준 최적화)

  • Kim, Jungseop;Jeong, Jiyong;Lee, Jonghwan
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.40 no.1
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    • pp.79-86
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    • 2017
  • This research focused on deciding optimal manufacturing WIP (Work-In-Process) limit for a small production system. Reducing WIP leads to stable capacity, better manufacturing flow and decrease inventory. WIP is the one of the important issue, since it can affect manufacturing area, like productivity and line efficiency and bottlenecks in manufacturing process. Several approaches implemented in this research. First, two strategies applied to decide WIP limit. One is roulette wheel selection and the other one is elite strategy. Second, for each strategy, JIT (Just In Time), CONWIP (Constant WIP), Gated Max WIP System and CWIPL (Critical WIP Loops) system applied to find a best material flow mechanism. Therefore, pull control system is preferred to control production line efficiently. In the production line, the WIP limit has been decided based on mathematical models or expert's decision. However, due to the complexity of the process or increase of the variables, it is difficult to obtain optimal WIP limit. To obtain an optimal WIP limit, GA applied in each material control system. When evaluating the performance of the result, fitness function is used by reflecting WIP parameter. Elite strategy showed better performance than roulette wheel selection when evaluating fitness value. Elite strategy reach to the optimal WIP limit faster than roulette wheel selection and generation time is short. For this reason, this study proposes a fast and reliable method for determining the WIP level by applying genetic algorithm to pull system based production process. This research showed that this method could be applied to a more complex production system.

A Design of Operational Test & Evaluation System for Weapon Systems thru Process-based Modeling (프로세스 기반의 모델링을 통한 무기체계 운용시험평가 시스템 설계)

  • Lee, Beom;Seo, Yoonho
    • Journal of the Korea Society for Simulation
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    • v.23 no.4
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    • pp.211-218
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    • 2014
  • The Test and Evaluation (T&E) system became more important due to its advancement and complexity of the weapon system. Time and cost saving T&E related studies are in progress mainly with advanced countries. By utilizing the Modeling and Simulation (M&S) technology recently, we may save time and money. Also, overcome security and safety limitations. There are many M&S based research activities in South Korea but it is way behind of the system that some countries already have developed. i.e.; United States. This area of study requires new way of developing strategies in the T&E system of Korea. This study is to design the Operational T&E system for weapon systems based on modeling of processes. And we modeled the processes of operational performance evaluation through utilizing resources and performance modules of weapon systems and combined it with the simulation engine for 3D visualization. Through this, we propose the Operational T&E system for weapon systems based on modeling of processes that represent operational performances visually.

PREDICTION OF DAILY MAXIMUM X-RAY FLUX USING MULTILINEAR REGRESSION AND AUTOREGRESSIVE TIME-SERIES METHODS

  • Lee, J.Y.;Moon, Y.J.;Kim, K.S.;Park, Y.D.;Fletcher, A.B.
    • Journal of The Korean Astronomical Society
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    • v.40 no.4
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    • pp.99-106
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    • 2007
  • Statistical analyses were performed to investigate the relative success and accuracy of daily maximum X-ray flux (MXF) predictions, using both multilinear regression and autoregressive time-series prediction methods. As input data for this work, we used 14 solar activity parameters recorded over the prior 2 year period (1989-1990) during the solar maximum of cycle 22. We applied the multilinear regression method to the following three groups: all 14 variables (G1), the 2 so-called 'cause' variables (sunspot complexity and sunspot group area) showing the highest correlations with MXF (G2), and the 2 'effect' variables (previous day MXF and the number of flares stronger than C4 class) showing the highest correlations with MXF (G3). For the advanced three days forecast, we applied the autoregressive timeseries method to the MXF data (GT). We compared the statistical results of these groups for 1991 data, using several statistical measures obtained from a $2{\times}2$ contingency table for forecasted versus observed events. As a result, we found that the statistical results of G1 and G3 are nearly the same each other and the 'effect' variables (G3) are more reliable predictors than the 'cause' variables. It is also found that while the statistical results of GT are a little worse than those of G1 for relatively weak flares, they are comparable to each other for strong flares. In general, all statistical measures show good predictions from all groups, provided that the flares are weaker than about M5 class; stronger flares rapidly become difficult to predict well, which is probably due to statistical inaccuracies arising from their rarity. Our statistical results of all flares except for the X-class flares were confirmed by Yates' $X^2$ statistical significance tests, at the 99% confidence level. Based on our model testing, we recommend a practical strategy for solar X-ray flare predictions.

Design and Implementation of Hi-speed/Low-power Extended QRD-RLS Equalizer using Systolic Array and CORDIC (시스톨릭 어레이 구조와 CORDIC을 사용한 고속/저전력 Extended QRD-RLS 등화기 설계 및 구현)

  • Moon, Dae-Won;Jang, Young-Beom;Cho, Yong-Hoon
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.47 no.6
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    • pp.1-9
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    • 2010
  • In this paper, we propose a hi-speed/low-power Extended QRD-RLS(QR-Decomposition Recursive Least Squares) equalizer with systolic array structure. In the conventional systolic array structure, vector mode CORDIC on the boundary cell calculates angle of input vector, and the rotation mode CORDIC on the internal cell rotates vector. But, in the proposed structure, it is shown that implementation complexity can be reduced using the rotation direction of vector mode CORDIC and rotation mode CORDIC. Furthermore, calculation time can be reduced by 1/2 since vector mode and rotation mode CORDIC operate at the same time. Through HDL coding and chip implementation, it is shown that implementation area is reduced by 23.8% compared with one of conventional structure.

Scheduling Technique for Remodeling Project of Inhabited Condition (재실 리모델링 특성을 반영한 공정계획 기법)

  • Paik, Hwa-Sook;Nam, Wook-Jin;Kim, Sung-Han;Kim, Hyung-Jin;Choi, Jong-Soo;Kim, Kyung-Hwan
    • Korean Journal of Construction Engineering and Management
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    • v.14 no.2
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    • pp.141-149
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    • 2013
  • This paper presents a scheduling technique that reflects various constraints in remodeling project of inhabited condition. The remodeling project of inhabited condition is required more detailed planning and control due to claims by noise, vibration, dust, smells, limited lift capacity, and limited temporary stock area. Because of the constraints, complexity in scheduling is increased and earlier completion is required to reduce the possibility of safety and environment accidents. Especially, in case of inhabited condition, the scheduling should be linked day-time/night-time/weekend work. This paper proposes a structured scheduling technique to incorporate those constraints in remodeling of inhabited condition. This scheduling technique considers not only remodeling process but also dismantling, newly-construction, and residents movement. Process expression method using MS-Project also presented to keep connectivity with existing scheduling system.

Hardware Design of High Performance ALF in HEVC Encoder for Efficient Filter Coefficient Estimation (효율적인 필터 계수 추출을 위한 HEVC 부호화기의 고성능 ALF 하드웨어 설계)

  • Shin, Seungyong;Ryoo, Kwangki
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.2
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    • pp.379-385
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    • 2015
  • This paper proposes the hardware architecture of high performance ALF(Adaptive Loop Filter) for efficient filter coefficient estimation. In order to make the original image which has high resolution and high quality into highly compressed image effectively and also, subjective image quality into improved image, the ALF technique of HEVC performs a filtering by estimating filter coefficients using statistical characteristics of image. The proposed ALF hardware architecture is designed with a 2-step pipelined architecture for a reduction in performance cycle by analysing an operation relationship of Cholesky decomposition for the filter coefficient estimation. Also, in the operation process of the Cholesky decomposition, a square root operation is designed to reduce logic area, computation time and computation complexity by using the multiplexer, subtracter and comparator. The proposed hardware architecture is designed using Xilinx ISE 14.3 Vertex-7 XC7VCX485T FPGA device and can support 4K UHD@40fps in real time at a maximum operation frequency of 186MHz.

Smoothing DRR: A fair scheduler and a regulator at the same time (Smoothing DRR: 스케줄링과 레귤레이션을 동시에 수행하는 서버)

  • Joung, Jinoo
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.19 no.1
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    • pp.63-68
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    • 2019
  • Emerging applications such as Smart factory, in-car network, wide area power network require strict bounds on the end-to-end network delays. Flow-based scheduler in traditional Integrated Services (IntServ) architecture could be possible solution, yet its complexity prohibits practical implementation. Sub-optimal class-based scheduler cannot provide guaranteed delay since the burst increases rapidly as nodes are passed by. Therefore a leaky-bucket type regulator placed next to the scheduler is being considered widely. This paper proposes a simple server that achieves both fair scheduling and traffic regulation at the same time. The performance of the proposed server is investigated, and it is shown that a few msec delay bound can be achieved even in large scale networks.

FPGA integrated IEEE 802.15.4 ZigBee wireless sensor nodes performance for industrial plant monitoring and automation

  • Ompal, Ompal;Mishra, Vishnu Mohan;Kumar, Adesh
    • Nuclear Engineering and Technology
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    • v.54 no.7
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    • pp.2444-2452
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    • 2022
  • The field-programmable gate array (FPGA) is gaining popularity in industrial automation such as nuclear power plant instrumentation and control (I&C) systems due to the benefits of having non-existence of operating system, minimum software errors, and minimum common reason failures. Separate functions can be processed individually and in parallel on the same integrated circuit using FPGAs in comparison to the conventional microprocessor-based systems used in any plant operations. The use of FPGAs offers the potential to minimize complexity and the accompanying difficulty of securing regulatory approval, as well as provide superior protection against obsolescence. Wireless sensor networks (WSNs) are a new technology for acquiring and processing plant data wirelessly in which sensor nodes are configured for real-time signal processing, data acquisition, and monitoring. ZigBee (IEEE 802.15.4) is an open worldwide standard for minimum power, low-cost machine-to-machine (M2M), and internet of things (IoT) enabled wireless network communication. It is always a challenge to follow the specific topology when different Zigbee nodes are placed in a large network such as a plant. The research article focuses on the hardware chip design of different topological structures supported by ZigBee that can be used for monitoring and controlling the different operations of the plant and evaluates the performance in Vitex-5 FPGA hardware. The research work presents a strategy for configuring FPGA with ZigBee sensor nodes when communicating in a large area such as an industrial plant for real-time monitoring.

Malware Detection Using Deep Recurrent Neural Networks with no Random Initialization

  • Amir Namavar Jahromi;Sattar Hashemi
    • International Journal of Computer Science & Network Security
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    • v.23 no.8
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    • pp.177-189
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    • 2023
  • Malware detection is an increasingly important operational focus in cyber security, particularly given the fast pace of such threats (e.g., new malware variants introduced every day). There has been great interest in exploring the use of machine learning techniques in automating and enhancing the effectiveness of malware detection and analysis. In this paper, we present a deep recurrent neural network solution as a stacked Long Short-Term Memory (LSTM) with a pre-training as a regularization method to avoid random network initialization. In our proposal, we use global and short dependencies of the inputs. With pre-training, we avoid random initialization and are able to improve the accuracy and robustness of malware threat hunting. The proposed method speeds up the convergence (in comparison to stacked LSTM) by reducing the length of malware OpCode or bytecode sequences. Hence, the complexity of our final method is reduced. This leads to better accuracy, higher Mattews Correlation Coefficients (MCC), and Area Under the Curve (AUC) in comparison to a standard LSTM with similar detection time. Our proposed method can be applied in real-time malware threat hunting, particularly for safety critical systems such as eHealth or Internet of Military of Things where poor convergence of the model could lead to catastrophic consequences. We evaluate the effectiveness of our proposed method on Windows, Ransomware, Internet of Things (IoT), and Android malware datasets using both static and dynamic analysis. For the IoT malware detection, we also present a comparative summary of the performance on an IoT-specific dataset of our proposed method and the standard stacked LSTM method. More specifically, of our proposed method achieves an accuracy of 99.1% in detecting IoT malware samples, with AUC of 0.985, and MCC of 0.95; thus, outperforming standard LSTM based methods in these key metrics.

Comparison of GMTI Performance Using DPCA for Various Clutters (DPCA를 이용한 지상 이동 표적 탐지에서 클러터 종류에 따른 성능 비교)

  • Lee, Myung-Jun;Lee, Seung-Jae;Kang, Byung-Soo;Ryu, Bo-Hyun;Lim, Byoung-Gyun;Oh, Tae-Bong;Kim, Kyung-Tae
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.28 no.6
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    • pp.487-496
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    • 2017
  • Ground moving target indicator(GMTI) using syntheticaperture radar(SAR) used for finding moving targets on wide background clutter in short time is one of good ways to monitor a traffic situation or an enemy's threat. Although displaced phase center antenna (DPCA) is a real time method with low computational complexity, there have been few studies about its performance against various ground clutters. Thus, we need to analyze GMTI performance for various ground clutters in order to design a suitable DPCA detector. In this paper, simulation results show that the conventional DPCA detector produces different performance in terms of detection rate and false alarm rate. In particular, the false alarm rate of heterogeneous or extremely heterogeneous clutter from urban area is higher than one of homogeneous clutter from natural area.