• ETRI Journal
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• v.37 no.6
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• pp.1143-1153
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• 2015

In this paper, we propose an efficient architecture for a real-time image stitching engine for vision SoCs found in motor vehicles. To enlarge the obstacle-detection distance and area for safety, we adopt panoramic images from multiple telegraphic cameras. We propose a stitching method based on a fixed homography that is educed from the initial frame of a video sequence and is used to warp all input images without regeneration. Because the fixed homography is generated only once at the initial state, we can calculate it using SW to reduce HW costs. The proposed warping HW engine is based on a linear transform of the pixel positions of warped images and can reduce the computational complexity by 90% or more as compared to a conventional method. A dual-core SW/HW image stitching engine is applied to stitching input frames in parallel to improve the performance by 70% or more as compared to a single-core engine operation. In addition, a dual-core structure is used to detect a failure in state machines using rock-step logic to satisfy the ISO26262 standard. The dual-core SW/HW image stitching engine is fabricated in SoC with 254,968 gate counts using Global Foundry's 65 nm CMOS process. The single-core engine can make panoramic images from three YCbCr 4:2:0 formatted VGA images at 44 frames per second and frequency of 200 MHz without an LCD display.

• The KIPS Transactions:PartC
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• v.9C no.1
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• pp.31-38
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• 2002

Communication systems, such as Switching System, are operated in the restricted conditions that the suggested events must finish in the time-constraints. Therefore, the data in the systems requires not only rapid access time, but also completion in the restricted time. Many existing data systems have been developed and used in the communication environments. But, the system construct a structural scheme and provide users with basic data services only. In recent, as the complexity of data in the communication area is rapidly increasing, it requires the data system which can represent the unstructured dataset and complete the data access in this dataset on the restricted condition. In this paper, we propose the data model which is suitable to the unstructured multi-dataset environment. The data model supports the rapid data access for unstructured dataset and enables users to easily retrieve data needed at the execution. In addition to, we define the several algorithms to clarify the structure of our model.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.397-400
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• 2016

In this paper, we propose an efficient algorithm for computing architecture for high-performance Inter Prediction SAD HEVC encoder. HEVC Motion Estimation (ME) of the Inter Prediction is a process for searching for the currently high prediction block PU and the correlation in the interpolated reference picture in order to remove temporal redundancy. ME algorithm uses full search(FS) or fast search algorithm. Full search technique has the guaranteed optimal results but has many disadvantages which include high calculation and operational time due to the motion prediction with respect to all candidate blocks in a given search area. Therefore, this paper proposes a new algorithm which reduces the computational complexity by reusing the SAD operation in full search to reduce the amount of calculation and computational time of the Inter Prediction. The proposed algorithm is applied to an HEVC standard software HM16.12. There was an improved operational time of 61% compared to the traditional full search algorithm, BDBitrate was decreased by 11.81% and BDPSNR increased by about 0.5%.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.459-461
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• 2022

One of the big differences between Network-on-Chip (NoC) and the existing parallel processing system based on an off-chip network is that data packet routing is performed using a centralized control scheme. In such an environment, the best-effort packet routing problem becomes a real-time assignment problem in which data packet arriving time and processing time is the cost. In this paper, the Hungarian algorithm, a representative computational complexity reduction algorithm for the linear algebraic equation of the allocation problem, is implemented in the form of a hardware accelerator. As a result of logic synthesis using the TSMC 0.18um standard cell library, the area of the circuit designed through case analysis for the cost distribution is reduced by about 16% and the propagation delay of it is reduced by about 52%, compared to the circuit implementing the original operation sequence of the Hungarian algorithm.

• Journal of Electrical Engineering and Technology
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• v.4 no.4
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• pp.559-565
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• 2009

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.104-110
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• 2008

In this paper, a novel 2-level-search sphere decoding algorithm for multiple-input multiple-output (MIMO) detection and its VLSI implementation are presented. The proposed algorithm extends the search space by concurrently performing symbol detection on 2 level of the tree search. Therefore, the possibility of discarding good candidates can be avoided. Simulation results demonstrate the good performance of the proposed algorithm in terms of bit-error-rate (BER). From the proposed algorithm, an efficient very large scale integration (VLSI) architecture which incorporates low-complexity and fixed throughput features is proposed. The proposed architecture supports many modulation techniques such as BPSK, QPSK, 16-QAM and 64-QAM. The sorting block, which occupies a large portion of hardware utilization, is shared for different operating modes to reduce the area. The proposed hardware implementation results show the improvement in terms of area and BER performance compared with existing architectures.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.28 no.6B
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• pp.683-690
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• 2008

The objectives of this study are to provide an observation-based urban flood prediction model and to evaluate their performance on a restored Cheonggye stream. The study area, which has its own unique hydrologic and flooding conditions that can be characterized the standard of flood occurrence by watergate opening and walk lane inundation, measured stream discharges at the 5 sites and watergate opening and walk lane inundation through the main stream since 2006. This study derived the relationship between precipitation intensity and watergate opening and walk lane inundation time by using the observations of 2006 and verified their performance on 2007 flood events. The result showed that the coefficients of determination are ranged on 0.57-0.75, which would be acceptable if considering the complexity of the area and the proposed model simplicity. It also suggested the continuous observation of these properties is required for further improvement of the models.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.34-45
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• 2007

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.

• Journal of the Korea Computer Graphics Society
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• v.22 no.3
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• pp.89-99
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• 2016

One of the fundamental elements in developing mixed reality applications is to effectively analyze and apply the environmental lighting information to image synthesis. In particular, interactive applications require to process dynamically varying lighting sources in real-time, reflecting them properly in rendering results. Previous related works are not often appropriate for this because they are usually designed to synthesize photorealistic images, generating too many, often exponentially increasing, light sources or having too heavy a computational complexity. In this paper, we present a fast light source estimation technique that aims to search for primary light sources on the fly from a sequence of video images taken by a camera equipped with a fisheye lens. In contrast to previous methods, our technique can adust the number of found light sources approximately to the size that a user specifies. Thus, it can be effectively used in Phong-illumination-model-based direct illumination or soft shadow generation through light sampling over area lights.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.84-95
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• 2006

In H/W implementation for the finite field the use of normal basis has several advantages, especially, the optimal normal basis is the most efficient to H/W implementation in $GF(2^m)$. In this paper, we propose a new, simpler, parallel multiplier over $GF(2^m)$ having a Gaussian normal basis of type k, which performs multiplication over $GF(2^m)$ in the extension field $GF(2^{mk})$ containing a type-I optimal normal basis. For k=2,4,6 the time and area complexity of the proposed multiplier is the same as tha of the best known Reyhani-Masoleh and Hasan multiplier.