• Journal of the Semiconductor & Display Technology
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• v.22 no.2
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• pp.128-132
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• 2023

Recently, with the development of deep learning technology, research on pedestrian attribute recognition technology using deep neural networks has been actively conducted. Existing pedestrian attribute recognition techniques can be obtained in such a way as global-based, regional-area-based, visual attention-based, sequential prediction-based, and newly designed loss function-based, depending on how pedestrian attributes are detected. It is known that the performance of these pedestrian attribute recognition technologies varies greatly depending on the type of backbone network that constitutes the deep neural networks model. Therefore, in this paper, several backbone networks are applied to the baseline pedestrian attribute recognition model and the performance changes of the model are analyzed. In this paper, the analysis is conducted using Resnet34, Resnet50, Resnet101, Swin-tiny, and Swinv2-tiny, which are representative backbone networks used in the fields of image classification, object detection, etc. Furthermore, this paper analyzes the change in time complexity when inferencing each backbone network using a CPU and a GPU.

• The KIPS Transactions:PartB
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• v.10B no.2
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• pp.143-150
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• 2003

Error concealment plays an important role in combating transmission errors. Methods of error concealment which produce better quality are generally of higher complexity, thus making some of the more sophisticated algorithms is not suitable for real-time applications. In this paper, we develop temporal and spatial error resilient video encoding and data hiding approach to facilitate the error concealment at the decoder. Block interleaving scheme is introduced to isolate erroneous blocks caused by packet losses for spatial area of error resilience. For temporal area of error resilience, data hiding is applied to the transmission of parity bits to protect motion vectors. To do error concealment quickly, a set of edge features extracted from a block is embedded imperceptibly using data hiding into the host media and transmitted to decoder. If some part of the media data is damaged during transmission, the embedded features are used for concealment of lost data at decoder. This method decreases a complexity of error concealment by reducing the estimation process of lost data from neighbor blocks. The proposed data hiding method of parity bits and block features is not influence much to the complexity of standard encoder. Experimental results show that proposed method conceals properly and effectively burst errors occurred on transmission channel like Internet.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.10
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• pp.907-911
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• 2006

In this paper, we propose a new structure that improves the on-state voltage drop and switching speed in Insulated Gate Bipolar Transistors(IGBTs), which can be widely used in high voltage semiconductors. The proposed structure is unique in that the collector area is divided by $SiO_2$, whereas the conventional IGBT has a planar P+ collector structure. The process and device simulation results show remarkably improved on-state and switching characteristics. Also, the current and electric field distribution indicate that the segmented collector structure has increased electric field near the $SiO_2$ corner, which leads to an increase of electron current. This results in a decrease of on-state resistance and voltage drop to $30%{\sim}40%$. Also, since the area of the P+ region is decreased compared to existing structures, the hole injection decreases and leads to an increase of switching speed to 30 %. In spite of some complexity in process procedures, this structure can be manufactured with remarkably improved characteristics.

• Journal of Institute of Control, Robotics and Systems
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• v.21 no.7
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• pp.621-626
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• 2015

This paper presents a camera calibration method in order to estimate the lane detection and inter-vehicle distance estimation system for an automotive safety driving system. In order to implement the lane detection and vision-based inter-vehicle distance estimation to the embedded navigations or black box systems, it is necessary to consider the computation time and algorithm complexity. The process of camera calibration estimates the horizon, the position of the car's hood and the lane width for extraction of region of interest (ROI) from input image sequences. The precision of the calibration method is very important to the lane detection and inter-vehicle distance estimation. The proposed calibration method consists of three main steps: 1) horizon area determination; 2) estimation of the car's hood area; and 3) estimation of initial lane width. Various experimental results show the effectiveness of the proposed method.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.2
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• pp.827-833
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• 2012

In this paper, we propose an improved optical flow algorithm which reduces computational complexity as well as noise level. This algorithm reduces computational time by applying level simplification technique and removes noise by using eigenvectors of objects. Optical flow is one of the accurate algorithms used to generate depth information from two image frames using the vectors which track the motions of pixels. This technique, however, has disadvantage of taking very long computational time because of the pixel-based calculation and can cause some noise problems. The level simplifying technique is applied to reduce the computational time, and the noise is removed by applying optical flow only to the area of having eigenvector, then using the edge image to generate the depth information of background area. Three-dimensional images were created from two-dimensional images using the proposed method which generates the depth information first and then converts into three-dimensional image using the depth information and DIBR(Depth Image Based Rendering) technique. The error rate was obtained using the SSIM(Structural SIMilarity index).

• Journal of the Korea Computer Graphics Society
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• v.5 no.2
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• pp.9-23
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• 1999

Visibility preprocessing is a useful method to reduce the complexity of scenes to be processed in real-time, and so enhances the overall rendering performance for interactive visualization of virtual environments. In this paper, we propose an efficient visibility preprocessing method. In the proposed method, we assume that navigatable areas in virtual environments are partitioned into rectangular parallelpiped cells or sub-worlds. To preprocess the visibility of each polygon for a given partitioned cell, we should determine at least the area-to-area visibility. This is inherently a four-dimensional problem. We efficiently express four-dimensional visibility information on two-dimensional spaces and keep it within a ternary tree, which is conceptually similar to a BSP(Binary Space Partitioning) tree, by exploiting the characteristics of conservative visibility. The proposed method is able to efficiently handle more general environments like urban scenes, and remove invisible polygons jointly blocked by multiple occluders. The proposed method requires O(nm) time and O(n+m) space. By selecting a suitable value for m, users can select a suitable level of trade-off between the preprocessing time and the quality of the computational result.

• Journal of Broadcast Engineering
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• v.15 no.4
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• pp.498-512
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• 2010

Intra coding is an indispensable coding tool since it can provide random accessibility as well as error resiliency. However, it is the problem that intra coding has relatively low coding efficiency compared with inter coding in the area of video coding. Even though H.264/AVC has significantly improved the intra coding performance compared with previous video standards, H.264/AVC encoder complexity is significantly increased, which is not suitable for low bit rate interactive services. In this paper, a Voting-based Intra Mode Bit Skip (V-IMBS) scheme is proposed to improve coding efficiency as well as to reduce encoding time complexity using decoder-side prediction. In case that the decoder can determine the same prediction mode as what is chosen by the encoder, the encoder does not send that intra prediction mode; otherwise, the conventional H.264/AVC intra coding is performed. Simulation results reveal a performance increase up to 4.44% overall rate savings and 0.24 dB in peak signal-to-noise ratio while the frame encoding speed of proposed method is about 42.8% better than that of H.264/AVC.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.50-59
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• 1998

This paper describes a 3.3V 8bit CMOS digital to analog converter (DAC) with two state current cell metrix architecture which consists of a 4 MSB and a 4 LSB current matrix stage. The symmetric two stage current cell matrix architecture allow the designed DAC to reduce hot only a complexity of decoding logics, but also a number of wider swing cascode curent mirros. The designed DAC with an active chip area of 0.8 mm$_{2}$ is fabricated by a 0.8 .mu.m CMOS n-well standard digital process. The experimental data shows that the rise/fall time, the settling time, and INL/DNL are6ns, 15ns, and a less than .+-.0.8/.+-.0.75 LB, respectively. The designed DAC is fully operational for the power supply down to 2.0V, such that the DAC is suitable for a low voltage and a low power system application. The power dissipation of the DAC with a single power supply of 3.3V is measured to be 34.5mW.

• 한국공간정보시스템학회:학술대회논문집
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• 2005.05a
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• pp.345-349
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• 2005

Massive amount of satellite image processing such asglobal/continental-level analysis and monitoring requires automated and speedy georegistration. There could be two major automated approaches: (1) rigid mathematical modeling using sensor model and ephemeris data; (2) heuristic co-registration approach with respect to existing reference image. In case of ETM+, the accuracy of the first approach is known as RMSE 250m, which is far below requested accuracy level for most of satellite image processing. On the other hands, the second approach is to find identical points between new image and reference image and use heuristic regression model for registration. The latter shows better accuracy but has problems with expensive computation. To improve efficiency of the coregistration approach, the author proposed a pre-qualified matching algorithm which is composed of feature extraction with canny operator and area matching algorithm with correlation coefficient. Throughout the pre-qualification approach, the computation time was significantly improved and make the registration accuracy is improved. A prototype was implemented and tested with the proposed algorithm. The performance test of 14 TM/ETM+ images in the U.S. showed: (1) average RMSE error of the approach was 0.47 dependent upon terrain and features; (2) the number average matching points were over 15,000; (3) the time complexity was 12 min per image with 3.2GHz Intel Pentium 4 and 1G Ram.

• Journal of Biomedical Engineering Research
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• v.28 no.6
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• pp.803-810
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• 2007

Although synthetic aperture focusing techniques can improve the spatial resolution of ultrasound imaging, they have not been employed in a commercial product because they require a real-time N-channel beamformer with a tremendously increased hardware complexity for simultaneous beamforming along M multiple lines. In this paper, a hardware-efficient beamformer architecture for synthetic aperture focusing is presented. In contrast to the straightforward design using NM delay calculators, the proposed method utilizes only M delay calculators by sharing the same values among the focusing delays which should be calculated at the same time between the N channels for all imaging points along the M scan lines. In general, synthetic aperture beamforming requires M 2-port memories. In the proposed beamformer, the input data for each channel is first upsampled with a 4-fold interpolator and each polyphase component of the interpolator output is stored into a 2-port memory separately, requiring 4M 2-port memories for each channel. By properly limiting the area formed with the synthetic aperture focusing, the input memory buffer can be implemented with only 4 2-port memories and one short multi-port memory.