• Title/Summary/Keyword: anti-aliasing filter

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Mixed CT/DT Cascaded Sigma-Delta Modulator

  • Lee, Kye-Shin
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.9 no.4
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    • pp.233-239
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    • 2009
  • A mixed CT/DT 2-1 cascaded ${\Sigma\Delta}M$ which includes a first stage CT ${\Sigma\Delta}M$ and a second stage mismatch insensitive two-channel time-interleaved DT ${\Sigma\Delta}M$ is proposed. With this approach, the advantages of both CT and DT ${\Sigma\Delta}Ms$ including high speed operation, inherent anti-aliasing filter, and good coefficient matching can be achieved. The two-channel time-interleaved ${\Sigma\Delta}M$ used in the second stage alleviates the speed constraints of the DT ${\Sigma\Delta}M$, whereas enables better matching between the analog and digital filter coefficients compared to CT ${\Sigma\Delta}Ms$.

A 9 mW Highly-Digitized 802.15.4 Receiver Using Bandpass ∑Δ ADC and IF Level Detection

  • Kwon, Yong-Il;Park, Ta-Joon;Lee, Hai-Young
    • Journal of electromagnetic engineering and science
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    • v.8 no.2
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    • pp.76-83
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    • 2008
  • A low power(9 mW) highly-digitized 2.4 GHz receiver for sensor network applications(IEEE 802.15.4 LR-WPAN) is realized by a $0.18{\mu}m$ CMOS process. We adopted a novel receiver architecture adding an intermediate frequency (IF) level detection scheme to a low-power complex fifth-order continuous-time(CT) bandpass L:tl modulator in order to digitalize the receiver. By the continuous-time bandpass architecture, the proposed $\Sigma\Delta$ modulator requires no additional anti-aliasing filter in front of the modulator. Using the IF detector, the achieved dynamic range(DR) of the over-all system is 95 dB at a sampling rate of 64 MHz. This modulator has a bandwidth of 2 MHz centered at 2 MHz. The power consumption of this receiver is 9.0 mW with a 1.8 V power supply.

A distance Relaying Algorithm Based on Numerical Solution of a Differential Equation for Transmission Line Protection (송전선 보호용 적분근사 거리계전 알고리즘)

  • 조경래;정병태;홍준희;박종근
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.43 no.5
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    • pp.711-720
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    • 1994
  • A distance relaying algorithm for detecting faults at power transmission line is presented in this paper. The algorithm is based on differential equation from relaton between voltage and current, which is composed of lumped resistance and inductance. During the fault transient state,the voltage and current signals are severely distorted due to the exponentially decaying DC offset and high frequency components, In spite of using small data, the presented integral method to evaluate R and L from voltage and current has high performance against these harmonics including DC offset. Therefore, the presented algorithm can be implemented with only a low order anti-aliasing analog filter and dosen't need any digital filter to remove specific components.

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Comparison of the characteristics of Distance Relaying Algorithms (거리계전 알고리즘별 특성 비교)

  • Kang, Sang-Hee;Lee, Seung-Jae;No, Jae-Keun;Yang, Eon-Pil;Jeong, Jong-Jin
    • Proceedings of the KIEE Conference
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    • 2001.05a
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    • pp.34-37
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    • 2001
  • This paper presents some results after comparing the characteristics of 3 algorithms, which are discrete Fourier transform based algorithm, least square method, and modified differential approximation algorithm, used at most distance relays all over the world. In case of the DFT based distance relaying algorithm, the length of the algorithm data window and the cut-off frequency of an anti-aliasing low-pass filter adopted are fixed. On the other hand, the data window lengths are changed according to the corresponding low-pass filters in the rest two algorithms. In series of tests, the apparent impedance estimated by the modified differential approximation algorithm shows faster and more stable characteristics of convergence than the two others.

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Development of the Digital Controller for High Precision Digital Power Supply (고정밀전원장치를 위한 디지털 제어기 개발)

  • Ha, K.M.;Lee, S.K.;Kim, Y.S.
    • Proceedings of the Korean Society of Marine Engineers Conference
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    • 2006.06a
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    • pp.249-250
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    • 2006
  • In this paper, hardware design and implementation of digital controller for the High Precision Digital Power Supply (HPDPS) based on Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) is presented. Developed digital controller is composed of high resolution Digital Pulse Width Modulation (DPWM) and high resolution analog to digital converter circuit with anti-aliasing filter. And Digital Signal Processor (DSP) has the capability of a few micro-second calculation time for one feedback loop. 32-bit DSP and DPWM with 150[ps] step resolution is used to implement the HPDPS. Also 18-bit 2 mega sample per second ADC board is adopted for the developed digital controller. Also, hardware structure of the developed digital controller and experimental results of the first prototype board for HPDPS is described.

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Design and Construction of a FFT Analyzer Using a Microcomputer (마이크로컴퓨터를 이용한 FFT 분석기의 설계 및 제작)

  • Lee, Hyeun Tae;Kim, Jung Gyu;Lee, Sang Bae
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.6
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    • pp.944-949
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    • 1986
  • By improving the ability of arithmatic processing with an arithmatic processor in a microcomputer and realizing the data input system for real time analysis, an FFT analyzer that is usable within the range of audio frequency is designed and constructed. The input signal passes through a gain programmable pre-amplifier and anti-aliasing lowpass filter into an analogditital converter to be converted into digital form. The converted input data is processed by an Apple II microcomputer. The results of the processing are displayed using a microcomputer display unit and can be copied on a printer or stored in a floppy disk.

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Modeling and Validation of 3DOF Dynamics of Maglev Vehicle Considering Guideway (궤도 선형을 고려한 자기부상 열차의 3자유도 동역학 모델 수립 및 검증)

  • Park, Hyeon-cheol;Noh, Myounggyu;Kang, Heung-Sik;Han, Hyung-Suk;Kim, Chang-Hyun;Park, Young-Woo
    • Journal of the Korean Society for Precision Engineering
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    • v.34 no.1
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    • pp.41-46
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    • 2017
  • Magnetically levitated (Maglev) vehicles maintain a constant air gap between guideway and car bogie, and thereby achieves non-contact riding. Since the straightness and the flatness of the guideway directly affect the stability of levitation as well as the ride comfort, it is necessary to monitor the status of the guideway and to alert the train operators to any abnormal conditions. In order to develop a signal processing algorithm that extracts guideway irregularities from sensor data, virtual testing using a simulation model would be convenient for analyzing the exact effects of any input as long as the model describes the actual system accurately. Simulation model can also be used as an estimation model. In this paper, we develop a state-space dynamic model of a maglev vehicle system, running on the guideway that contains jumps. This model contains not only the dynamics of the vehicle, but also the descriptions of the power amplifier, the anti-aliasing filter and the sampling delay. A test rig is built for the validation of the model. The test rig consists of a small-scale maglev vehicle, tracks with artificial jumps, and various sensors measuring displacements, accelerations, and coil currents. The experimental data matches well with those from the simulation model, indicating the validity of the model.